
************************************************************************
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**                                                                    **
**                 Application notes for Ramtron devices              **
**                                                                    **
**                       (Informal Document)                          **
**                                                                    **
**   To find the application notes for your device search for the     **
**   'core' part name.  As an example using the FM25L256 8 pin SOIC   **
**   you would search this document for the entry "25L256"            **
**                                                                    **
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 24CL04
 ----------
 25040
 ----------
 25CL64
 ----------
 25256
 ----------
 25L256
 ----------
 25640
 ----------
 
 There are four levels of Block Protection that can be supported
 on these devices:

                                          Start/End Block
                         (BP1), (BP0)   Protection Addresses
 Security Fuse settings:   SF2,   SF1      25040/24CL04
 ------------------------------------   --------------------
                             0,     0      None        
                             0,     1      $0300->$03FF
                             1,     0      $0200->$03FF
                             1,     1      $0000->$03FF
 ----------------------------------------------------------------

                                           Start/End Block
                         (BP1), (BP0    Protection Addresses
 Security Fuse settings:   SF2,   SF1        25CL64
 ------------------------------------   --------------------
                             0,     0      None
                             0,     1      $1800->$1FFF
                             1,     0      $1000->$1FFF
                             1,     1      $0000->$1FFF
 ----------------------------------------------------------------

                                           Start/End Block
                         (BP1), (BP0)    Protection Addresses
 Security Fuse settings:   SF2,   SF1      25256/25L256
 ------------------------------------   --------------------
                             0,     0      None        
                             0,     1      $6000->$7FFF
                             1,     0      $4000->$7FFF
                             1,     1      $0000->$7FFF
 ----------------------------------------------------------------

                                           Start/End Block
                         (BP1), (BP0)   Protection Addresses
 Security Fuse settings:   SF2,   SF1        25640
 ------------------------------------   --------------------
                             0,     0      None
                             0,     1      $1800->$1FFF
                             1,     0      $1000->$1FFF
                             1,     1      $0000->$1FFF
 ----------------------------------------------------------------

 Enabling the "Erase EE device" option will ONLY remove all block protection.

 NOTE: The "Erase EE device" option must be enabled when re-programming
       the device in order to remove the Block Protection.

 NOTE: The "Erase EE device" option will NOT Erase the device. 
       To re-program the device you must disable Blank/Illegal Bit
       checks flags.

 To program the Hardware Write Protection option (WPEN) enable
 the "Program protect reg." flag.

 Performing a Load operation will also load the Status Register
 Protection Bits into the following address locations in User RAM:
 25CL64  = Address $2000
 25640   = Address $2000
 25256   = Address $8000
 25L256  = Address $8000

 The data format in the Programmer's User RAM will follow the same
 format as defined in the corresponding device's data sheet.

 Status Register Format in relation to the Protection Bits:
  -------------------------------------------------------
 |Bit 7 |Bit 6 |Bit 5 |Bit 4 |Bit 3 |Bit 2 |Bit 1 |Bit 0 |
 |-------------------------------------------------------|
 | WPEN |  X   |  X   |  X   | BP1  | BP0  |  X   |  X   |
  -------------------------------------------------------

***********************************************************************


