PSD TESTS MENU
--------------
 	1.  Utilities/
 	2.  Node Tests/
 	3.  Message Network Tests/
 	4.  MIO Module Tests/
 	5.  SCSI Device Tests/
 	6.  HiPPI Module Tests/

NOTE:  The back slash (/) immediately following a test name indicates
       that the test is a directory and that there are a series of
       tests contained within that directory.  Any test without a
       back slash indicates an individual test.


MIO MODULE TESTS
----------------

   The MIO Module Test menu contains tests which verify the MIO Module.

        1.  RAM Data Line Test
        2.  RAM Address Test
        3.  RAM Moving Inverse Test
        4.  SCSI Controller Test


RAM Data Line Test
   The RAM Data Line Test verifies the data lines to location zero
   in the MIO Module RAM. Patterns 0x0000, 0xffff, 0xf0f0, 0xcccc,
   0x3333, 0x5555, 0xaaaa, and 0x0000 are written, read, and verified.

RAM Address Test
   The RAM Address Test verifies the address lines to the MIO Module
   RAM. Incrementing data corresponding to address lines 0 through
   17 is written to Bank 1. Addresses used are 0, 1, 2, 4, 8, 0x10,
   0x20, 0x40, 0x80, 0x100, 0x200, 0x400, 0x800, 0x1000, 0x2000, 0x4000,
   0x8000, 0x10000, 0x20000, and 0x3ffff. Data written to the locations
   is, respectively, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
   14, 15, 16, 17, 18, and 19. Incrementing data corresponding to
   address lines 0 through 17 is written to Bank 2. Addresses used
   are 0x40000, 0x40001, 0x40002, 0x40004, 0x40008, 0x40010, 0x40020,
   0x40040, 0x40080, 0x40100, 0x40200, 0x40400, 0x40800, 0x41000,
   0x42000, 0x44000, 0x48000, 0x50000, 0x60000, and 0x7fffff. Data
   written to the locations is, respectively, 20, 21, 22, 23, 24,
   25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, and 39.
   All these addresses are now read and the received data compared
   to the expected patterns. If an Ethernet is installed on this MIO,
   data is not written or read from the top 64K bytes of the MIO RAM.

RAM Moving Inverse Test
   The RAM Moving Inverse Test verifies the 512K bytes of MIO Module
   RAM.The entire RAM is initialized with pattern 0x0000. Bank 1(addresses
   0x80000000-0x8003ffff) is tested first. The first location of RAM
   is read to verify the previously written pattern. The first location
   is written with new pattern 0xffff. The first location is read
   to verify the previously written pattern. This read, verify, write,
   read, and verify is repeated for every word in the first bank of
   RAM. The above sequence is repeated with patterns 0xf0f0, 0xcccc,
   0x3333, 0x5555, 0xaaaa, and 0x0000.

   The above sequence is repeated for bank 2(addresses 0x80040000
   - 0x8007ffff). Bank 2 is only tested for addresses 0x80040000 -
   0x8006ffff on the boot node or any node with active ethernet. The
   ethernet is alive at this point and superfluous data can occur
   in the upper 64K bytes of MIO RAM.

SCSI Controller Test
   The SCSI Controller Test verifies the functionality of the SCSI
   Controller and Xilinx DMA. The reset, configuration registers,
   illegal command interrupt, DMA, FIFO count, and FIFO overflow functions
   are tested.


