Notes on the timing considerations for Nevermore.

Alastair Bridgewater, 2004-Mar-21.


This will be a quick one. Mostly just operation frequencies of
various parts of the Explorer system.

The microinstruction cycle is given to be 142 nanoseconds. That
is about 7 million cycles per second.

Two of the three interval timers on the SIB board are driven at
1 million cycles per second, or once every 7 microinstructions.

The SIB RTC has a base cycle time of 100 nanoseconds, which is
somewhat unfortunate. This is, however, sufficiently fast that
it is unlikely that we will need much precision of simulation
at this level. The next rate that the RTC has available at the
register level is 10 milliseconds, which is equivalent to every
7000 microinstructions. One might well ask what happened to the
one millisecond clock and all of the microsecond-based clocks.

The SIB RTC is supposedly fed from a 32768 Hz crystal, which
suggests that the 100 nanosecond clock register might be poorly
documented at best. The extended diagnostic also appears to
trash the RTC registers. It would be interesting to see if the
SIB self-test documentation mentions that facet of the extended
diagnostics, since if it doesn't it might imply that there is
another location where the present time is stored.

Now the question is how to deal with simulating this mess. The
simplest option is probably just to have a list of functions to
call before every microinstruction and have them each maintain
counters for how many cycles they need to run before anything
has to happen on their end.

EOF
