Section 1 Introduction
IBM Reference Products
Reference Design
Reference Boards and Systems
Reference Firmware
Purpose
Differences Between Release 1.0, 3.0 and 4.0
Processor Cards
Other CEC Functions
IBM27-82660 Bridge
L2 Cache
System Memory
PCI Bus
SCSI Controller
Network Support AMD AM79C970A (Ethernet)
Multi-Processor Interrupt Controller (MPIC)
Flash ROM
PCI/ISA Bridge Chip
Business Audio
Native I/O Controller National PC87332 Super I/O
X Bus
Time of Day Clock
PS/2 Compatible Keyboard/Mouse Controller
System I/O EPLD
System Clocks
Section 2 CPU Bus
CPU Busmasters
CPU Bus Arbitration
Fast L2/Data Streaming Mode (No-DRTRY#)
CPU Bus Frequency
Bi-Endian Mode Operation
System Response by CPU Bus Transfer Type
System Response by CPU Bus Address Range
Address Mapping for Contiguous I/O
Address Mapping for Non-Contiguous I/O
PCI Final Address Formation
LE Mode
CPU to PCI Read
CPU to PCI Write
Eight-Byte Writes to the PCI (Memory and I/O)
CPU to PCI Memory Transactions
CPU to PCI I/O Transactions
CPU to PCI Configuration Transactions
CPU to PCI Interrupt Acknowledge Transaction
PCI Locks and CPU Reservations
CPU to ROM Read
CPU to ROM Write
ROM Write Protection
CPU to BCR Transfers
CPU Slot Signal Descriptions
CPU Slot DC Characteristics
CPU Slot AC Timing
CPU Slot Power Supplies
CPU Slot Thermal Envelope
CPU Slot Card Connector
Auxiliary CPU Slot Connectors
L2 Tag/SRAM Interface (L2 Slot)
L2 Slot ID ROM
L2 Cache ID ROM Signaling Interface
L2 Slot Signal Descriptions
L2 Slot DC Characteristics
L2 Slot AC Timing
L2 Slot Power Supplies
L2 Slot Thermal Envelope
L2 Slot Dual Voltage Capability
L2 Slot Connector
L2 Slot Pin Assignments
Electrical Model of Major Signal Groups
Motherboard Electrical Model
CPU Card and L2 Card Interface Models
CPU Card Model
L2 Card Model
660 Bridge Electrical Model
Model Building
Section 3 Endian Mode Considerations
The 604 Address Munge
The 604 Data Shift
The 660 Bridge Address Unmunge
The 660 Bridge Data Swapper
Bit Ordering Within Bytes
Byte Swap Instructions
604 CPU Alignment Exceptions In LE Mode
Single-Byte Transfers
Two-Byte Transfers
Four-Byte Transfers
Three byte Transfers
Instruction Fetches and Endian Modes
Changing BE/LE Mode
Summary of Bi-Endian Operation and Notes
Section 4 CPU Card
PowerPC 604 Processor
JTAG/RISCWatch Interface
J2 Auxiliary Test Connector
Fansink
Bus Clock Skew Circuit
2.5v Power Supply
Presence Detect Bits
DRVMOD Bits
Additional Bits
Electrical and Thermal Requirements
Absolute Maximum Ratings
DC Specifications
Thermal
AC Timing Requirements
Electrical Model of Major Signal Groups
Pin Definitions
Section 5 DRAM and ROM
Memory Controller (DRAM)
Organization
Refresh
DRAM Presence Detection
DRAM Bank Rules
PCI Bus ROM
Remote ROM
ROM Read, Write, and Write Protect
Section 6 Exceptions
PCI interrupt handling
ISA interrupt handling
CPU to CPU Interrupt Handling
PCI Interrupt Assignments
ISA Interrupt Assignments
Scatter/Gather (SG) Interrupts
SCSI Bus Interrupts
MCP# Considerations
SMI# Considerations
HRESET# Logic
JTAG Interface Hard Resets
HRESET PAL Equations
SRESET Logic
SRESET PAL equations
SMP Reset Considerations
Hard Reset
Hard Reset Phase 1
Hard Reset Phase 2
Hard Reset Phase 3
Soft Reset
Data Error Checking
CPU to Memory Writes
CPU to Memory Reads
PCI to Memory Parity Errors
CPU to PCI Transaction Data Parity Errors
Illegal CPU cycles
SERR, I/O Channel Check, and NMI Logic
Out of Bounds PCI Memory Accesses
No Response on CPU to PCI Cycles - Master Abort
CPU to PCI Cycles That Are Target Aborted
Error Status Registers
Reporting Error Addresses
Errant Masters
Special Events Not Reported as Errors
Section 7 Clocks
CPU Card Clock Repeater
CPU Clock Physical Design Rules
CPU Clock Control Logic
Clock Logic Input - J17
Clock Logic Input - CPU Slot PD Bits
Clock Logic Output - CPU Bus Clock Frequency Select
Clock Logic Output - 604 PLL Configuration
Clock Logic Transfer Function
Frequency Select PAL Equations
Clock Freezing
PCI Bus speed Selection
Oscillators, Crystals, and Clocks
Section 8 PCI Bus
PCI Transaction Decoding By Bus Command
PCI Memory Transaction Decoding By Address Range
PCI I/O Transaction Decoding
ISA Master Considerations
Bus Snooping on PCI to Memory Cycles
PCI Peer to PCI Peer Transactions
PCI to System Memory Transactions
PCI Configuration Transactions
650 Bridge Compatible Method
PCI Bus Loading
Section 9 ISA and X-Bus
Address Ranges
ISA Bus Concurrency
ISA Busmasters and IGN_PCI_AD31
Supported DMA Paths
DMA Timing
Scatter-Gather
Keyboard/Mouse Control Registers
RTC Address and NMI Enable Register
RTC Data Register
NVRAM Address Register Low
NVRAM Address Register High
NVRAM Data Register
Motherboard Presence Detect Registers
Floppy Media Sense ID
Equipment Presence Register
L2 ID Register
Motherboard ID Register
CPU ID Registers
DRAM ID Registers
Section 10 System EPLD
Storage Light Register
System Control Register 081C
Power Management Control Registers
Power Management Control Register 1
Power Management Control Register 2
IRQ13 Interrupt Request Active Register (Not Supported)
Freeze Clock Registers
Freeze Clock Register (FCR) Low
Freeze Clock Register (FCR) High
Serial ROM Control Register
Serial ROM Communications Protocol
Serial ROM vs. PD bits
L2 Control Register
CPU Sequence Register
CPU Enable Register
External Hardware Reset
Section 11 I/O Subsystems
Ethernet Physical and Electrical Design Guidelines
Ethernet Power and Ground Guidelines
Ethernet 10BASE-T Layout Guidelines
Ethernet Oscillator Guidelines
Ethernet Sleep Mode
SCSI Physical and Electrical Design Guidelines
SCSI Component Location
SCSI Bus Routing
SCSI Decoupling
SCSI Impedance Matching
SCSI EMC Considerations
SCSI Termination
Cable/Device Presence Detect
SCSI Interrupts
Audio Performance
Audio Connector Specifications
Audio Control Registers
Audio Index Register
Audio Indexed Data Register
Audio Status Register
Audio PIO Data Register
The CS4232 Logical Device
Control Register 0
Control Register 1
Joystick Port
SoundBlaster Registers
MPU-401 MIDI
MIDI Status Register
Section 12 System Firmware
Introduction
Boot Record
PC Partition Table Entry
Extended DOS Partition
PowerPC Reference Platform Partition Table Entry
Loading the Load Image
System Console
System Initialization
Main Menu
System Configuration Menu
Run a Program
Reprogram Flash Memory
Exit Options
Default Configuration Values
Section 13 Registers and System Setup
Fast L2/Data Streaming Mode (No-DRTRY#)
CPU to PCI Configuration Transactions
Preferred Method of Generating PCI Configuration Transactions
650 Bridge Compatible Method
PCI Configuration Scan
Multi-Function Adaptors
PCI to PCI Bridges
660 Bridge Indexed BCR Summary
ISA Bridge (SIO) Initialization
ISA Bridge PCI Configuration Registers
MPIC PCI Configuration Registers
MPIC PCI I/O Registers
MPIC Global Registers (PCI I/O)
MPIC Interrupt Source Configuration Registers (PCI I/O)
MPIC Per Processor Registers (PCI I/O)
Ethernet PCI Configuration Registers
Ethernet PCI I/O Registers
Ethernet CSR and BSR Registers
Ethernet EEPROM Interface
SCSI PCI Configuration Registers
SCSI PCI I/O Registers
SuperI/O Pin Strap Configuration
SuperI/O Configuration Register Configuration
SuperI/O Controller Register Access
SuperI/O FDC Registers
SuperI/O UART Registers
SuperI/O Parallel Port Registers
SuperI/O IDE Registers
CS4232 Initialization
Config State
Device
ADDRESS0, ADDRESS1, ADDRESS2
INT0, INT1
DMA0, DMA1
ACTIVATE
WAIT_FOR_KEY
Reference Design Combined Register Listing
ISA Registers
Direct Access ISA Registers
Section 14 Riser
Dual Bus Riser Connector Features
Special Comments about Riser and Motherboard Wiring
3.3v, 6-Pin Connector for PCI Slots
Current Capacity of Connectors on the Riser
PCI Connector (On Riser)
3.3v, 6-Pin Connector (On Riser)
ISA Connector (On Riser)
Section 15 Power
External Power Supply Requirements
Power Supply Current Requirements
Power Supply Power Requirements
Additional Power Supply Requirements
Onboard 3.6v Regulator
Section 16 Mechanical
System Layout
System 3D Sheet 1
System 3D Sheet 2
System Layout - Rear Panel Connector Locations
Motherboard Component Locator
Motherboard Mounting Holes
Motherboard Header and Jumper Locations
Motherboard Connector Locations
Motherboard Connector Details - Sheet 1 of 2
Motherboard Connector Details - Sheet 2 of 2
CPU Card 3D Views
CPU Card Layout
CPU Card Fansink Assembly
Riser Mechanical
Riser Details
Motherboard L2 Card Connector for 5v Tolerant Systems
Outline Drawing of 5v Output L2 Card
Motherboard L2 Card Connector for 3.3v Only Systems
Outline Drawing of 3.3v Output L2 Card
Section 17 Connectors
Connector Locations
Battery Connector BATTERY
DRAM SIMM Connectors J0, J1, J2, J3, J4, J5, J6, J7
Mouse Connector J10
Keyboard Connector J11
Power Connector J13
Riser Connector J14
External SCSI Device Connector J19
Ethernet 10BASE-T Connector J21
CD-ROM Connector J22
Momentary On-Off Power Switch Connector J23 (Not Used)
Parallel Connector J25
Serial Port 1 (External) Connector J26
Serial Port 2 (Internal) Connector J27
Power Up Configuration Jumper J28
AUX5/ON-OFF Connector J29
Speaker Connector J31 and J39
Internal SCSI Device Connector J32
Game Port Connector J33
Fansink Connectors J34, J36, J43, J45
Box Fan Connector J37
Reset Switch Connector J38
Line In Jack J40
Power Good LED Connector J41
Floppy Diskette Drive (FDD) Connector J42
HDD LED Connector J44
Microphone Jack J46
Line Out Jack J47
Headphone Jack J48
Internal/FaxModem Connector J49
Riser 3.3v Power Connector J50
Riser 3.3v Power Cable
3.3v Power Connector J51
Section 18 Physical Design Guidelines
Motherboard Construction
Riser Construction
Cheetah3 Board Construction
Clock Wires
Noise Sensitive Wires
To Be Run With Adjacent Grounds
To Be Run With No Wires in Adjacent Channels
CEC Critical Wires
L2 Cache Critical Wires
PCI Critical Control Wires
PCI Address/Data Wires
SCSI I/O Wires
Audio I/O Wires
Input/Output Wires
Ethernet Wires
Memory Wires
Battery Wires
Fan Wires
8mm Tape Contents and Extract Instructions
Download Instructions
Cadence Version
Tape Contents
Section 19 Bills of Materials
Section 20 Updates
Configuration for 603 1:1 or 3:2 Mode
Section 21 Schematics
Section 22 Data Sheets