Section 1
System EPLD

The System EPLD (EPLD) supports registers and logic which are needed by the system and are not contained in any other device. It provides glue logic, internal control registers, and control signals to access external control registers. Most applications will use a customized version of the EPLD to handle their unique requirements.

The EPLD is a programmed Alterat EPM5130QC100 electrically programmable logic device. For timing and electrical specifications, see that data sheet.

The EPLD supports both internal (contained in the EPLD) and external (contained in other devices) registers.

1.1 External Registers

For the external registers that the EPLD supports, Table 1 shows the external register, the ISA I/O port address, and the supplied control signal(s). Motherboard Presence Detect Registers in the ISA and X-Bus section contains descriptions of these registers.

Table 1. External Register Support
ISA Port Address	Register	Read/ Write	Register Location	Signal	Strobe or Function
0060 or 0062 or 0064 or 0066	Keyboard Controller Registers	R/W	Keyboard Controller	KYBD_CS# (asserted for an ac cess to any of these addresses)	Address Decode
0070	RTC Address Latch Enable	W/O	RTC	RTC_ALE	Write strobe
0071	RTC Data	Write	RTC	RTC_WR#	Write strobe
		Read		RTC_RD#	Read strobe
0074	NVRAM Address Low Byte	W/O	NVRAM	RTC_AS0#	Address Decode
0075	NVRAM Address High Byte	W/O	NVRAM	RTC_AS1#	Address Decode
0077	NVRAM Data	Write	NVRAM	NVRAM_WR#	Write Strobe
		Read		NVRAM_RD#	Read Strobe
03F3	Floppy Media Sense	R/O	FDC U27	RD_3F3#	Read Strobe
080C	Equipment Present Reg.	R/O	Board U23	EQP_PRSNT_RD#	Read Strobe
080D	L2 ID Register	R/O	Board U23	CACHE_PD_RD#	Read Strobe
0852	Motherboard ID Register	R/O	Board U29	PLANAR_ID_RD#	Read Strobe
0866	CPU 1 ID Register	R/O	Board U28	PROC1_PD_RD#	Read Strobe
0867	CPU 2 ID Register	R/O	Board U56	PROC2_PD_RD#	Read Strobe
0880	DRAM ID Registers 0	R/O	Board U58	DRAM_PD_RD#	Read Strobe
0881	DRAM ID Registers 1	R/O	Board U52	DRAM_PD_RD#	Read Strobe
0882	DRAM ID Registers 2	R/O	Board U54	DRAM_PD_RD#	Read Strobe
0883	DRAM ID Registers 3	R/O	Board U53	DRAM_PD_RD#	Read Strobe

1.2 Internal Registers

Table 2. Internal Register Support
ISA Port Address	Register	Access	Note
0808	Storage Light Register	Read/Write
081C	System Control Register	Read/Write	1
082A	Power Management Control Register 1	Read/Write
082B	Power Management Control Register 2	Read/Write
0838	IRQ13 Interrupt Request Active Register	Read/Write
0860	Freeze Clock Register Low	Write
0862	Freeze Clock Register High	Write
0868	Serial ROM Control Register	Read/Write
086B	L2 Control Register	Write
0870	CPU Sequence Register	Read
0871	CPU Enable Register	Write
Note: Except bits 2:0 (W/O). This register is shared with the 660 Bridge System Control 81C BCR.

1.2.1 Storage Light Register

Bit 0 Hard Disk Activity Light:
0 = Turn light off (negate HDD_LED#).
1 = Turn light on (assert HDD_LED#).

1.2.2 System Control Register 081C

Bit 1:0 DMA Select[1:0] - These bits select which DMA channel is used by the ECP function. These bits are write only. See Table 3.

Bit 2 DMA Select Enable - This bit enables or disables the ECP DMA function. If this bit is 0, then no DMA channel is allocated to the parallel port. This bit is write only. See Table 3.

Table 3. External Register Support
Bit 2	Bit 1	Bit 0	ECP DMA Channel	ECPA#	ECPB#	ECPC#	ECPD#
0	x	x	None	1	1	1	1
1	0	0	0	0	1	1	1
1	0	1	1	1	0	1	1
1	1	0	3	1	1	0	1
1	1	1	5	1	1	1	0

The ECPx# outputs are asserted continuously, and are used on the motherboard to enable tristate buffers that do the actual routing of the DMA request.

Bit 3 Floppy Controller Motor Select Disable - This bit enables/disables the MTR0# and MTR1# motor select signals driven by the floppy disk controller. Disabling these signals allows the user to read media sense information without spinning up the drive motor.
0 = Enable MTR0# and MTR1# (assert FD_MTR_EN#)
1 = Disable MTR0# and MTR1# (negate FD_MTR_EN#).

Bit 4 L2 Flush - If there is an external lookaside L2 in the system, this bit can be used to flush it.
0 = Drive L2_FLUSH# low.
1 = Drive L2_FLUSH# high.

Bit 5 Reserved.

Bit 6 L2 Cache Disable - This bit will disable an external cache but will not invalidate the contents. While disabled, the L2 will not respond to any cycles.
0 = L2 Cache Disable (assert L2_CACHE_DIS#).
1 = L2 Cache Enable (negate L2_CACHE_DIS#).

Bit 7 L2 Cache Miss Inhibit - This bit is intended to prevent L2 misses from updating an external L2. This allows the external L2 to retain its contents during memory accesses and remain coherent.
0 = Prevent updates (assert L2_CACHE_INH#)
1 = Normal operation (negate L2_CACHE_INH#).

1.2.3 Power Management Control Registers

1.2.4 Power Management Control Register 1

Bit 0 Data Bit - This bit is the serial data to and from the 83C750 power management controller (PMC).

Bit 3:1 PMC Command [2:0] - PMC command

Bit 4 I/O Strobe - This bit strobes the serial data in and out of the 83C750 PMC.

Bit 7:5 Reserved

1.2.5 Power Management Control Register 2

Bit 0 Reset Power Management Controller - This bit is used by POST to guarantee the state of the PM Controller on every Power-On Reset.
0 = Writing a 0 to this bit causes the EPLD to negate 83CX_RESET.
1 = While this bit is a 1, the EPLD asserts 83CX_RESET to the PMC. It is the
responsibility of the host to hold the reset long enough to meet the
specification of the PM Controller. This bit is not reset to `0' by RESET# signal.

1.2.6 IRQ13 Interrupt Request Active Register (Not Supported)

This register exists to allow power management systems and primary IDE to share one system interrupt. Power management and IDE are both unsupported on the reference design. This information is for evaluation purposes only.

Bit 0 Primary IDE Interrupt Request Active - When read, this bit indicates status of the primary IDE interrupt request. When an external primary IDE device has driven the system interrupt request signal active, this bit is set to 1 and remains set to 1 until software clears the condition by setting the bit to 0 or by the RESET# signal. Writing a 1 to this bit has no effect.

Bit 7:1 Reserved

1.2.7 Freeze Clock Registers

To use the registers, first write the low register, and then the high register. Writing the high register triggers a write operation. The FCR data in ports 0860 and 0862 is shifted out as a serial data stream on FRZ_DATA. Initially, FRZ_DATA will be set to zero and then it will start shifting13 times. At the end of the shifting, FRZ_DATA will stay at 1.

After triggering the data transfer, wait at least 10 usec. for the transfer to complete before accessing the FCR or retriggering the data transfer.

A 0 in a bit position of the port 0860 or 0862 instructs the MPC970 to freeze the corresponding clock output of the MPC970 and a 1 in that bit position instructs the MPC970 to unfreeze the clock output.

On the reference design, this data transfer is clocked by a 1.843MHz oscillator. For details of the data transfer operation and the meaning of the data, see the MPC970 data sheet.

1.2.7.1 Freeze Clock Register (FCR) Low

ISA Port 0860

Write Only

Reset to FFh

Bit	Reference Design Clock Consumer
0	CPU Slot 1_2 (BCLK 2)
1	CPU Slot 2_2 (BCLK 2)
2	664 BCLK
3	CPU Slot 2_0 (BCLK 0)
4	CPU Slot 2_1 (BCLK 1)
5	CPU Slot 1_0 (BCLK 0)
6	CPU Slot 1_1 (BCLK 1)
7	L2 Slot (Tag) (Tag BCLK) See Freeze Clock Register (FCR) High.

1.2.7.2 Freeze Clock Register (FCR) High

ISA Port 0862

Write Only

Reset to xxx1 1111

Bit	Reference Design Clock Consumer
0	SRAM_BCLK0
1	SRAM_BCLK1
2	SRAM_BCLK2
3	SRAM_BCLK3
4	Spares (PALs) (MC_BCLK_SPARE)

Bit 7:5 Reserved

1.2.8 Serial ROM Control Register

ISA Port 0868

Read/Write

Reset to 0000 xx10

Bit 0 Serial ROM Clock - This bit sets the state (non-inverted) of the SER_CLK output. The clock is toggled manually by setting this bit high and low. While the clock is 'running,' maintain the frequency from 0 to 500kHz.

Bit 1 Serial ROM Clock Disable - The serial clock shares a net with the PD bits of the CPU and L2 cards.
0 = Assert SER_CLK_EN# to enable external buffers to drive the serial clock
onto the PD0 lines of the CPU and L2 slots.
1 = Negate SER_CLK_EN# to disable the external buffers.

Bit 3:2 Reserved

Bit 4 Serial ROM Data Direction - The serial ROM data bit I/Os share PD lines with the CPU and L2 cards. In input mode, these I/Os do not interfere with the PD bits.
0 = Input - Direction of data flow is in to the EPLD from the serial ROM.
1 = Output - Direction of data flow is out from the EPLD to the serial ROM.

Bit 5 CPU Card 1 Serial ROM Data Bit - This is a bidirectional signal.
Output = This bit sets the state (non-inverted) of the PC1_DATA output.
Input = This bit reports the state (non-inverted) of the PC1_DATA input.

Bit 6 CPU Card 2 Serial ROM Data Bit - This is a bidirectional signal.
Output = This bit sets the state (non-inverted) of the PC2_DATA output.
Input = This bit reports the state (non-inverted) of the PC2_DATA input.

Bit 7 L2 Cache Serial ROM Data Bit - This is a bidirectional signal.
Output = This bit sets the state (non-inverted) of the L2_DATA output.
Input = This bit reports the state (non-inverted) of the L2_DATA input.

1.2.8.1 Serial ROM Communications Protocol

The serial communication protocol used by the L2 and CPU card ID ROM is defined as follows. One start bit followed by an eight bit control byte then a returned eight bits of data. The control byte consists of a two bit command (1,0 for reads), a four bit address A[3:0], and two don't care bits (x,x). The four bit address selects which of the 16 bytes to read.

Start

1

0

A3

A2

A1

A0

X

X

D7

D6

D5

D4

D3

D2

D1

D0

The start bit consists of a falling edge on SDA while SCLK is held high. With the exception of the start bit, all transitions on SDA occur while SCLK is low. The read cycle is driven on the bus as shown in Figure 2.

1.2.8.2 Serial ROM vs. PD bits

The serial ROM clock shares a net with L2_PD[0] from each CPU slot and SRAM_PD[0] of the L2 slot. The serial ROM clock enable controls external buffers that gate the clock onto these lines. The same enable controls all three buffers (see SER_CLK_EN# on the schematics).

When not reading or testing for the presence of a serial ROM, leave the serial ROM clock disabled, and leave the serial ROM data bit I/Os configured as inputs.

The PD bits on the cards are implemented with pulldown and pullup resistors (e.g., 10k pullup and 100 ohm pulldown) instead of by shorting the lines to ground or VCC. When reading the serial ROM(s), enable the clock and read the ROM quickly, then disable the clock. In this way, the electronics of cards that have implemented are not subject to increased current draw for long enough for significant heating to occur.

1.2.9 L2 Control Register

Bit 0 L2 Cache WT/WB
0 = L2 Cache must operate in write through mode (L2_WT# is asserted)
1 = L2 Cache is allowed to operate in write back mode (L2_WT# is negated).

Bit 1 L2 Cache Configuration Decode
0 = L2 Cache Configuration is enabled (L2_CONF_DCD# is asserted)
1 = L2 Cache Configuration is disabled (L2_CONF_DCD# is negated)

Bit 7:2 Reserved

1.2.10 CPU Sequence Register

Bit 1:0 CPU Sequence bits[1:0]

Bit 7:2 Reserved

This register provides CPUs with a way to get a unique CPU number in an SMP system. Bits 1:0 form a binary counter.

• The first time after reset that the counter is read, it reports 00b. At the end of the read, it increments to 01b.
• The next read returns 01b, and the counter post-increments to 10b.
• The next read returns 10b, and the counter post-increments to 11b.
• The next and all subsequent reads of this register return 11b.

1.2.11 CPU Enable Register

Bit 0 CPU A1 Disable #
1 = Set PROC_A1_DIS# high
0 = Set PROC_A1_DIS# low. See Note.

Bit 1 CPU B1 Disable #
1 = Set PROC_B1_DIS# high.
0 = Set PROC_B1_DIS# low. See Note.

Bit 2 CPU A2 Disable #
1 = Set PROC_A2_DIS# high.
0 = Set PROC_A2_DIS# low. See Note.

Bit 3 CPU B2 Disable #
1 = Set PROC_B2_DIS# high.
0 = Set PROC_B2_DIS# low. See Note.

Bit 7:4 Reserved

Note: When D[3:0] = 0000 during a write to this port, the EPLD will set all four PROC_x_DIS# outputs high.

1.2.11.1 External Hardware Reset

If D[3:0] = 0000 during a write to this port while the RESET# input is deasserted, then the EPLD will pulse the EXTHRST# output low. EXTHRST# is asserted for 1024 cycles of the PWR_MNG_CLK.

EXTHRST# is normally connected to the HRESET# circuit on the motherboard, such that it acts in parallel to an external reset push button.

1.3 Signal Descriptions

Table 4. Signal Descriptions
Signal Name	Pin	I/O	Description
External Register Support
CACHE_PD_RD#	8	O 6mA	L2 presence detect read strobe. EPLD asserts this sig nal to read X-bus port 080D.
DRAM_PD_RD#	90	O 6mA	DRAM SIMM presence detect read enable 1. EPLD as serts this signal to read X-bus ports 0880-0883.
EQP_PR_RD#	79	O 6mA	Equipment present register read. EPLD asserts this signal to read X-bus port 080C.
KYBD_CS#	52	O 6mA	Keyboard chip select. EPLD asserts this signal to read X-bus ports 0060, 0062, 0064, and 0066.
NVRAM_RD#	75	O 6mA	NVRAM output enable (read strobe). EPLD asserts this signal to read X-bus port 0077. This normally causes a read of the NVRAM data stored at the location contained in the NVRAM address register.
NVRAM_WR#	34	O 6mA	NVRAM data write strobe. EPLD asserts this signal to write to X-bus port 0077. This normally causes the data associated with this write to be written into the NVRAM location contained in the NVRAM address register.
PLANAR_ID_RD#	33	O 6mA	Planar ID read. EPLD asserts this signal to read X-bus port 0852.
PROC1_PD_RD#	7	O	CPU 1 Card Present Detect Read: EPLD asserts this signal to read X-bus port 0866.
PROC2_PD_RD#	6	O	CPU 2 Card Present Detect Read: EPLD asserts this signal to read X-bus port 0867.
RTC_ALE#	57	O 6mA	Real time clock address latch enable. EPLD asserts this signal to write X-bus port 0070.
RTC_AS0#	24	O 6mA	NVRAM address register low byte write strobe. EPLD asserts this signal to write to X-bus port 0074.
RTC_AS1#	23	O 6mA	NVRAM address register high byte write strobe. EPLD asserts this signal to write to X-bus port 0075.
RTC_RD#	32	O 6mA	Real time clock read strobe. EPLD asserts this signal to read X-bus port 0071.
RTC_WR#	31	O 6mA	Real time clock write strobe. EPLD asserts this signal to write to X-bus port 0071.
ISA and X-bus
ECPA#	89	O	Printer DMA request: This signal enables external logic to route the ECP DMA Request to DMA channel 0.
ECPB#	86	O	Printer DMA request: This signal enables external logic to route the ECP DMA Request to DMA channel 1.
ECPC#	85	O	Printer DMA request: This signal enables external logic to route the ECP DMA Request to DMA channel 3.
ECPD#	84	O	Printer DMA request: This signal enables external logic to route the ECP DMA Request to DMA channel 5.
ECS[2:0]	59, 22, 21	I	Encoded Chip Select [2:0]. Encoded chip selects for pe ripheral devices supported by the ISA I/O Bridge. Used by EPLD X-bus I/O port address decoders. From SIO.
ECSEN#	60	I	Encoded Chip Select Enable. Asserted to enable the base decoder. Negated to select the option decoder. Used by EPLD X-bus I/O port address decoders. From SIO.
ISA_CLK	26	I	ISA Clock: The ISA bus clock.
ROM_EN#	45	O	ROM Chip Enable: This signal is the chip select for the system boot ROM when it is located on the ISA bus.
XA[7:0]	61 ,64, 65, 66, 67, 70, 71, 72.	I	X-address bus [7:0]. Used by EPLD X-bus I/O port ad dress decoders.
XD[7:0]	73,92,95, 96,97,74, 98,99	I/O 24mA	X-data bus [7:0]. Used by EPLD to transfer data.
XIOR#	9	I	X-bus I/O Read. Indicates that the system is reading from an X-bus I/O device. Used by EPLD X-bus I/O port ad dress decoders.
XIOW#	16	I	X-bus I/O Write. Indicates that the system is writing to an X-bus I/O device. Used by EPLD X-bus I/O port address decoders.
Interrupts
IRQ1_IN	14	I	Keyboard interrupt. EPLD is designed to intercept the keyboard interrupt between the keyboard and the ISA bus bridge. It is monitored in the suspend state as a wakeup indicator. Either connect IRQ1_SIO and IRQ1_IN as shown in the reference design, or disconnect both signals from the system (routing the keyboard interrupt to the ISA bus bridge).
IRQ1SIO	56	O	Interrupt request 1. Latched active when IRQ1_IN is as serted. Negated when KYBD_CS# is asserted.
IRQ12	15	I	Interrupt request 12 input. Connect to system IRQ12, the mouse interrupt. It is monitored in the suspend state as a wakeup indicator.
Floppy Disk Interface
RD_3F3#	25	O	Media Sense Read: The EPLD asserts this signal during reads to ISA port 03F3. This signal is used to enable mo therboard logic to drive SD[7:4]. The SuperI/O also inter nally decodes reads of this register and drives information onto SD[3:0]. See the SuperI/O data book.
FD_MTR_EN#	1	O	Motor Enable:This active low output pin is used to dis able MTR0# and MTR1# signals from the SuperI/O chip, and is controlled by Port 081C, bit 3.
HDD_LED#	83	O 6mA	Hard disk drive activity light. EPLD asserts this signal while bit 0 of the storage light register (port 0808) is 1. This signal normally indicates hard disk drive activity.
L2 Cache Interface
L2_CACHE_DIS#	81	O	L2 cache disable: This output can be used to disable an external L2. It is controlled by bit 6 of Port 081C.
L2_CACHE_INH#	76	O	L2 cache inhibit: This output can be used to inhibit an external L2. It is controlled by bit 7 of Port x`081C'.
L2_CONF_DCD#	82	O	L2 configuration decode: This active low output is used to enable configuration mode in certain serial L2 caches.
L2_FLUSH#	51	O	L2 cache flush: This signal follows the value written to System Control BCR 0 (address 8000 081Ch bit 4): while bit 4 is 0, L2_FLUSH# will be asserted. It can be used to flush an external L2 cache.
L2_WT#	3	O	L2 write through: This active low output can be used to force an external L2 into write through only mode.
SMP Interface (see the CPU Sequence Register)
HALT1	27	I	Halt 1: This active high signal indicates that a CPU on CPU card 1 is asserting HALT. Also see RUN.
HALT2	28	I	Halt 2: This active high signal indicates that a CPU on CPU card 2 is asserting HALT. Also see RUN.
PROC_A1_DIS#	35	O	Processor A1 enable: This active low output is used to force the assertion of HRESET# to CPU A in CPU card 1.
PROC_B1_DIS#	36	O	Processor B1 enable: This active low output is used to force the assertion of HRESET# to CPU B in CPU card 1.
PROC_A2_DIS#	39	O	Processor A2 enable: This active low output is used to force the assertion of HRESET# to CPU A in CPU card 2.
PROC_B2_DIS#	40	O	Processor B2 enable: This active low output is used to force the assertion of HRESET# to CPU B in CPU card 2.
RUN	2	O	Run: This active high output is routed to each CPU. RUN enables the CPU to snoop and conduct bus operations. The EPLD negates RUN only while HALT1 and HALT2 are both active. All of the CPUs in the system have to assert HALT for RUN to be negated.
SEMIFOR_ST#	46	O	Semaphore status: This normally high output pulses low during accesses to the CPU sequence register.
Serial ROM Interface (see the Serial ROM Control Register)
L2_DATA	53	I/O	L2 Cache Card Serial Data: This is a bidirectional pin used for L2 card serial data.
PC1_DATA	55	I/O	Processor Card 1 Serial Data: This is a bidirectional pin used for processor card 1 serial data.
PC2_DATA	54	I/O	Processor Card 2 Serial Data: This is a bidirectional pin used for processor card 2 serial data.
SER_CLK	78	O	Serial Clock: This is the clock output for serial ROM.
SER_CLKEN	29	O	Serial Clock Enable: This active high output enables buffers to drive the serial clock onto PD0 of each card.
System Clock Interface
FRZ_DATA	49	O	Freeze data out. Serial data stream to MPC970 clock chip. See the MPC970 data sheet.
PWR_MNG_CLK	20	I	Power Management clock. Used to clock the freeze seri al data stream from EPLD to the MPC970 clock chip. See the MPC970 data sheet connected to ISA_CLK.
Power Management (not supported in release 1.0)1
83CX_RESET	91	O 6mA	PMC reset. Resets the PMC. EPLD asserts this signal while bit 0 of Port 082B (Power Management Control Reg ister 2) is a 1 (see note 1).
ACTIVITY#	30	O 6mA	Activity. EPLD asserts this signal to alert the PMC that system activity (mouse or keyboard) is occurring. No-con nect or connect as shown (see note 1).
CMD_STATE#	10	I	PMC command state. Indicates that the PMC is in the command state. No-connect or connect as shown (see note 1).
IO_STROBE#	100	O	I/O strobe. EPLD asserts this signal to the PMC while 83CX_RESET is low and bit 4 of Port 082A (Power Man agement Control Register 1) is high. No-connect or con nect as shown (see note 1).
PROC_RDY	50	I	PMC ready. Indicates that the PMC is in the ready state. No-connect or connect as shown (see note 1).
RWD0	48	I/O 24mA	PMC serial read/write data bit. This Is the bi-directional serial data line between the EPLD and the PMC. No-con nect or connect as shown (see note 1).
SUSACK#	17	I	Suspend ACK: This active low input from the ISA bridge indicates that the system is ready to go into suspend mode. This signal is not used with the Intel SIO - instead it is connected to SUSREQ#.
SUSREQ#	80	O	Suspend request: This active low output indicates that suspend has been requested. This signal is not used with the Intel SIO - instead it is connected to SUSACK#.
UNFREEZE	47	I	Unfreeze. The PMC asserts this signal to EPLD to tell EPLD to unfreeze the clocks. No-connect or connect as shown (see note 1).
Reserved Pins
HFCS0#	77	O	Reserved Function.
HFCS1#	58	O	Reserved Function.
IDEIRQP	5	I	Reserved Function.
RSVD_BIDI1	42	I /O	Reserved BIDI 1: This is reserved BIDI.
RSVD_IN	41	I	Reserved Input: This is a reserved input.
Other Signals
EXTHRST#	4	O(3S)	External Hard Reset: This signal is tristate while deas serted. It is driven low for 1024 cycles of the PWR_MGN_CLK to reset the system. See CPU Enable Register.
RESET#	11	I	System reset. Used by EPLD to reset internal state ma chines and internal registers. Also see CPU Enable Regis ter.
GND	12, 13, 37, 38, 62, 63, 87, 88	I	Ground.
VCC	18, 19, 43, 44, 68, 69, 93, 94	I	+5v:
Note: Power management is not supported on the reference design. The descriptions of the above signals show how to connect those signals if the power management circuits are removed from the board.

1.4 EPLD Design Equations

%*****************************************************************%
%*********  AHDL  SOURCE CODE FOR KEYSTONE  V1.8   ***************%
%*****************************************************************%

          DESIGN IS "kstnsio"
          BEGIN
              DEVICE "kstnsio" IS "EPM5130WC-1"
              BEGIN
                  A0                             @  72     : INPUT ;
                  A1                             @  71     : INPUT ;
                  A2                             @  70     : INPUT ;
                  A3                             @  67     : INPUT ;
                  A4                             @  66     : INPUT ;
                  A5                             @  65     : INPUT ;
                  A6                             @  64     : INPUT ;
                  A7                             @  61     : INPUT ;
                  /CMDSTATE                      @  10     : INPUT ;
                  /ECSEN                         @  60     : INPUT ;
                  ECS2                           @  59     : INPUT ;
                  ECS1                           @  22     : INPUT ;
                  ECS0                           @  21     : INPUT ;
                  /SUSACK                        @  17     : INPUT ;
                  IDEIRQP                        @   5     : INPUT ;
                  HALT1                          @  27     : INPUT ;
                  HALT2                          @  28     : INPUT ;
                  IRQ1                           @  14     : INPUT ;
                  IRQ12                          @  15     : INPUT ;
                  PWR_MNG_CLK                    @  20     : INPUT ;
                  PROC_RDY                       @  50     : INPUT ;
                  /RESET                         @  11     : INPUT ;
                  /UNFREEZE                      @  47     : INPUT ;
                  /XIOR                          @   9     : INPUT ;
                  /XIOW                          @  16     : INPUT ;
                  RSVD_IN                        @  41     : INPUT ;
                  ISA_CLK                        @  26     : INPUT ;

                  /ACTIVITY                      @  30     : OUTPUT;
                  /SUSREQ                        @  80     : OUTPUT;
                  /CACHE_PD_RD                   @   8     : OUTPUT;
                  /PROC1_PD_RD                   @   7     : OUTPUT;
                  /PROC2_PD_RD                   @   6     : OUTPUT;
                  /DRAM_PD_RD                    @  90     : OUTPUT;
                  /ECPA                          @  89     : OUTPUT;
                  /ECPB                          @  86     : OUTPUT;
                  /ECPC                          @  85     : OUTPUT;
                  /ECPD                          @  84     : OUTPUT;
                  /EQP_PR_RD                     @  79     : OUTPUT;
                  FRZ_DATA                       @  49     : OUTPUT;
                  /HDD_LED                       @  83     : OUTPUT;
                  /HFCS0                         @  77     : OUTPUT;
                  /HFCS1                         @  58     : OUTPUT;
                  RUN                            @   2     : OUTPUT;
                  /IO_STROBE                     @ 100     : OUTPUT;
                  /KYBD_CS                       @  52     : OUTPUT;
                  /L2_CACHE_DIS                  @  81     : OUTPUT;
                  /L2_CACHE_INH                  @  76     : OUTPUT;
                  /L2_FLUSH                      @  51     : OUTPUT;
                  /L2_WT                         @   3     : OUTPUT;
                  /L2_CONF_DCD                   @  82     : OUTPUT;
                  /MOTOR_EN                      @   1     : OUTPUT;
                  /NVRAM_RD                      @  75     : OUTPUT;
                  /NVRAM_WR                      @  34     : OUTPUT;
                  /PLANAR_ID_RD                  @  33     : OUTPUT;
                  /RD_3F3                        @  25     : OUTPUT;
                  /RTC_AS0                       @  24     : OUTPUT;
                  /RTC_AS1                       @  23     : OUTPUT;
                  /RTC_RD                        @  32     : OUTPUT;
                  /RTC_WR                        @  31     : OUTPUT;
                  83CX_RESET                     @  91     : OUTPUT;
                  /ROM_EN                        @  45     : OUTPUT;
                  /PROC_A1_DIS                   @  35     : OUTPUT;
                  /PROC_B1_DIS                   @  36     : OUTPUT;
                  /PROC_A2_DIS                   @  39     : OUTPUT;
                  /PROC_B2_DIS                   @  40     : OUTPUT;
                  /SEMIFOR_ST                    @  46     : OUTPUT;
                  SER_CLK                        @  78     : OUTPUT;
                  SER_CLKEN                      @  29     : OUTPUT;
                  /RTC_ALE                       @  57     : OUTPUT;
                  IRQ1SIO                        @  56     : OUTPUT;
                 /EXTHRST                        @   4     : OUTPUT;

                  PC1_DATA                       @  55     : BIDIR ;
                  PC2_DATA                       @  54     : BIDIR ;
                  L2_DATA                        @  53     : BIDIR ;
                  RWD0                           @  48     : BIDIR ;
                  XD0                            @  99     : BIDIR ;
                  XD1                            @  98     : BIDIR ;
                  XD2                            @  74     : BIDIR ;
                  XD3                            @  97     : BIDIR ;
                  XD4                            @  96     : BIDIR ;
                  XD5                            @  95     : BIDIR ;
                  XD6                            @  92     : BIDIR ;
                  XD7                            @  73     : BIDIR ;
                  RSVD_BIDI1                     @  42     : BIDIR ;
              END;
          END;

SUBDESIGN KSTNSIO
(
%****************************************************************%
%        DEFINE PRIMARY INPUTS AND OUTPUTS                      *%
%****************************************************************%

%---------------------  Inputs ---------------------%

        /SUSACK                         :INPUT;
        ECS[2..0]                       :INPUT;
        /ECSEN                          :INPUT;
        A[7..0]                         :INPUT;
        /XIOR                           :INPUT;
        /XIOW                           :INPUT;
        /RESET                          :INPUT;
        PWR_MNG_CLK                     :INPUT;
        IRQ1                            :INPUT;
        IRQ12                           :INPUT;
        IDEIRQP                         :INPUT;
        HALT1                           :INPUT;
        HALT2                           :INPUT;
        PROC_RDY                        :INPUT;
        /CMDSTATE                       :INPUT;
        /UNFREEZE                       :INPUT;
        ISA_CLK                         :INPUT;
        RSVD_IN                        :INPUT;

%---------------  Bidirectional Outputs ------------%

        XD[7..0]                        :BIDIR;
        RWD0                            :BIDIR;
        PC2_DATA                        :BIDIR;
        PC1_DATA                        :BIDIR;
        L2_DATA                         :BIDIR;
        RSVD_BIDI1                      :BIDIR;

%--------------------- Outputs  --------------------%

        /EQP_PR_RD                      :OUTPUT;
        /CACHE_PD_RD                    :OUTPUT;
        /PROC1_PD_RD                    :OUTPUT;
        /PROC2_PD_RD                    :OUTPUT;
        /PLANAR_ID_RD                   :OUTPUT;
        /DRAM_PD_RD                     :OUTPUT;
        /ROM_EN                         :OUTPUT;
        /MOTOR_EN                       :OUTPUT;
        /RD_3F3                         :OUTPUT;
        /ECPA                           :OUTPUT;
        /ECPB                           :OUTPUT;
        /ECPC                           :OUTPUT;
        /ECPD                           :OUTPUT;
        /HDD_LED                        :OUTPUT;
        /KYBD_CS                        :OUTPUT;
        /RTC_RD                         :OUTPUT;
        /RTC_WR                         :OUTPUT;
        /RTC_AS0                        :OUTPUT;
        /RTC_AS1                        :OUTPUT;
        /NVRAM_WR                       :OUTPUT;
        /NVRAM_RD                       :OUTPUT;
        /HFCS0                          :OUTPUT;
        /HFCS1                          :OUTPUT;
        RUN                             :OUTPUT;
        FRZ_DATA                        :OUTPUT;
        83CX_RESET                      :OUTPUT;
        /ACTIVITY                       :OUTPUT;
        /IO_STROBE                      :OUTPUT;
        /SUSREQ                         :OUTPUT;
        /L2_CACHE_DIS                   :OUTPUT;
        /L2_CACHE_INH                   :OUTPUT;
        /L2_FLUSH                       :OUTPUT;
        /L2_CONF_DCD                    :OUTPUT;
        /L2_WT                          :OUTPUT;
        SER_CLK                         :OUTPUT;
        SER_CLKEN                       :OUTPUT;
        /SEMIFOR_ST                     :OUTPUT;
        /PROC_A1_DIS                    :OUTPUT;
        /PROC_B1_DIS                    :OUTPUT;
        /PROC_A2_DIS                    :OUTPUT;
        /PROC_B2_DIS                    :OUTPUT;
        /RTC_ALE                        :OUTPUT;
        IRQ1SIO                         :OUTPUT;
        /EXTHRST                        :OUTPUT;
)

VARIABLE

        PSWD1_PRTCTFF          :SRFF;
        PSWD2_PRTCTFF          :SRFF;
        RTC_BLKFF              :SRFF;
        HDD_LEDFF              :SRFF;
        CTL_REG0[7..0]         :SRFF;
        PWR_REG2               :SRFF;
        SHIFT_ENFF             :SRFF;
        START_SHIFTFF          :SRFF;
        IDE_REG[0]             :DFF;
        CNTR[3..0]             :DFF;
        CNTRRST[9..0]          :DFF;
        STARTCNTR1             :DFF;
        /FREEZE                :DFF;
        CLKFF[12..0]           :DFFE;
        SNC_SHIFT_ENFF          :DFFE;
        PROC_A1                 :DFF;
        PROC_B1                 :DFF;
        PROC_A2                 :DFF;
        PROC_B2                 :DFF;
        PROC_SEQ[1..0]          :DFF;
        CMDSTATE_FF             :DFF;
        RSVD_INFF               :DFF;
        SER_REG[5..0]           :DFF;
        L2_CR[1..0]             :DFF;
        SEMIFOR_STFF            :DFF;
        IRQ1SIO_FF              :DFF;

        RWD0_BUFF               :TRI;
        EXTRST                  :TRI;

        DATA0                   :NODE;
        D[7..0]                 :NODE;
        XD_TRI_OE               :NODE;
        EN800_8FF               :NODE;
        RTC_BLK_FLG             :NODE;
        FDC_CS                  :NODE;
        LIGHT_EN                :NODE;
        CTL_REG0_EN             :NODE;
        83CX_CS                 :NODE;
        PWR_REG1_EN             :NODE;
        PWR_REG2_EN             :NODE;
        IDE_REG_EN              :NODE;
        CLKFF_WR                :NODE;
        CLKFF_SELL              :NODE;
        CLKFF_SELH              :NODE;
        GEN_START_BIT           :NODE;
        GEN_STOP_BIT            :NODE;
        STOP_SHIFT              :NODE;
        PROC_SEQ_RD             :NODE;
        PROC_EN                 :NODE;
        PROC_EN_WR              :NODE;
        L2_CR_EN                :NODE;
        L2_CR_WR                :NODE;
        SER_EN                  :NODE;
        SER_REG_WR              :NODE;
        IRQ1SIO_EN0             :NODE;
        IRQ1SIO_EN1             :NODE;
        IRQ1SIO_RST             :NODE;

BEGIN

/KYBD_CS  = !(!ECS[2] & ECS[1] & !ECS[0] & !/ECSEN);

/RTC_RD  = !(!RTC_BLKFF.q & !ECS[2] & !ECS[1] & !/ECSEN & !A[2]
           & !A[1] & A[0] & !/XIOR);

/RTC_WR = !(!RTC_BLKFF.q & !ECS[2] & !ECS[1] & !/ECSEN & !A[2]
          & !A[1] & A[0] & !/XIOW);

/RTC_AS0 = !(!ECS[2] & !ECS[1] & !/ECSEN & A[2] & !A[1] & !A[0] 
	   & !/XIOW);

/RTC_AS1 = !(!ECS[2] & !ECS[1] & !/ECSEN & A[2] & !A[1] & A[0]
           & !/XIOW);

/NVRAM_WR = !(!ECS[2] & !ECS[1] & !/ECSEN & A[2] & A[1] & A[0]
	    & !/XIOW);

/NVRAM_RD = !(!ECS[2] & !ECS[1] & !/ECSEN & A[2] & A[1] & A[0]
	    & !/XIOR);

RTC_BLK_FLG     =  PSWD1_PRTCTFF.Q & XD[5] & !XD[4]
                 # PSWD2_PRTCTFF.Q & XD[5] &  XD[4];
RTC_BLKFF.s     = RTC_BLK_FLG & !A[2] & !A[1] & !A[0] & !ECS[2]
		 & !ECS[1] & !/XIOW;
RTC_BLKFF.r     = !RTC_BLK_FLG & !A[2] & !A[1] & !A[0] & !ECS[2]
		 & !ECS[1] & !/XIOW;
RTC_BLKFF.clk   = /ECSEN;
RTC_BLKFF.clrn  = /RESET;

/RTC_ALE = !ECS[2] & !ECS[1] & !/ECSEN & !A[2] & !A[1]
           & !A[0] & !/XIOW;

/HFCS0 = !(!ECS[2] & !ECS[1] & !ECS[0] & !/ECSEN); % 1F0 - 1F7 %

/HFCS1 = !(!ECS[2] & !ECS[1] &  ECS[0] & !/ECSEN); % 3F6 - 3F7 %

/ROM_EN = !(ECS[2] & !ECS[1] & !ECS[0] & !/ECSEN);

FDC_CS = ECS[2] & !ECS[1] & !ECS[0] & !/ECSEN ;

/RD_3F3 = !(FDC_CS & A[7] & A[6] & A[5] & A[4] & !A[3]
          & !A[2] & A[1] & A[0] & !/XIOR);

EN800_8FF = !ECS[2] & ECS[1] & !ECS[0] & /ECSEN ;

/DRAM_PD_RD  = !(EN800_8FF & A[7] & !A[6] & !A[5] & !A[4]
               & !A[3] & !A[2] & !/XIOR);

LIGHT_EN = EN800_8FF & !A[7] & !A[6] & !A[5] & !A[4]
           & A[3] & !A[2] & !A[1] & !A[0];

HDD_LEDFF.s     = LIGHT_EN & XD[0];
HDD_LEDFF.r     = LIGHT_EN & !XD[0];
HDD_LEDFF.clk   =  /XIOW;
HDD_LEDFF.clrn  = /RESET;

/HDD_LED        = !HDD_LEDFF.q ;

/EQP_PR_RD      = !(EN800_8FF & !A[7] & !A[6] & !A[5] & !A[4]
                  & A[3] & A[2] & !A[1] & !A[0] & !/XIOR);

/CACHE_PD_RD    = !(EN800_8FF & !A[7] & !A[6] & !A[5] & !A[4]
                   & A[3] & A[2] & !A[1] & A[0] & !/XIOR);

/PROC1_PD_RD    = !(EN800_8FF & !A[7] & A[6] & A[5] & !A[4]
                  & !A[3] & A[2] & A[1] & !A[0] & !/XIOR);

/PROC2_PD_RD    = !(EN800_8FF & !A[7] & A[6] & A[5] & !A[4]
                  & !A[3] & A[2] & A[1] & A[0] & !/XIOR);

L2_CR_EN  =   EN800_8FF & !A[7] & A[6] & A[5] & !A[4] & A[3] & !A[2]
            & A[1] & A[0];

L2_CR_WR  = L2_CR_EN & !/XIOW;

L2_CR[0].prn  = VCC;
L2_CR[0].clrn = /RESET;
L2_CR[0].clk  = !L2_CR_WR;
L2_CR[0].d    = L2_CR_EN & XD[0];

L2_CR[1].prn  = /RESET;
L2_CR[1].clrn = VCC;
L2_CR[1].clk  = !L2_CR_WR;
L2_CR[1].d    = L2_CR_EN & XD[1];

/L2_WT       = L2_CR[0].q & /RESET;
/L2_CONF_DCD = L2_CR[1].q & /RESET;

SER_EN  =  EN800_8FF & !A[7] & A[6] & A[5] & !A[4] & A[3] & !A[2]
         & !A[1] & !A[0];

SER_REG_WR  = SER_EN & !/XIOW;

SER_REG[0].prn  = VCC;
SER_REG[0].clrn = /RESET;
SER_REG[0].clk  = !SER_REG_WR;
SER_REG[0].d    =  XD[0];

SER_CLK         = SER_REG[0].q;

SER_REG[1].prn  = /RESET;
SER_REG[1].clrn = VCC;
SER_REG[1].clk  = !SER_REG_WR;
SER_REG[1].d    =  XD[1];

SER_CLKEN       = !SER_REG[1].q;

SER_REG[2].prn  = VCC;
SER_REG[2].clrn = /RESET;
SER_REG[2].clk  = !SER_REG_WR;
SER_REG[2].d    =  XD[4];

SER_REG[3].prn  = VCC;
SER_REG[3].clrn = /RESET;
SER_REG[3].clk  = !SER_REG_WR;
SER_REG[3].d    = XD[5];

SER_REG[4].prn  = VCC;
SER_REG[4].clrn = /RESET;
SER_REG[4].clk  = !SER_REG_WR;
SER_REG[4].d    = XD[6];

SER_REG[5].prn  = VCC;
SER_REG[5].clrn = /RESET;
SER_REG[5].clk  = !SER_REG_WR;
SER_REG[5].d    = XD[7];

PC1_DATA        = TRI(SER_REG[3].q, SER_REG[2].q);
PC2_DATA        = TRI(SER_REG[4].q, SER_REG[2].q);
L2_DATA         = TRI(SER_REG[5].q, SER_REG[2].q);

PROC_SEQ_RD =  EN800_8FF & !A[7] & A[6] & A[5] & A[4] & !A[3] & !A[2]
             & !A[1] & !A[0] & !/XIOR;

PROC_SEQ[1..0].prn       = VCC;
PROC_SEQ[1..0].clk       = !PROC_SEQ_RD;
PROC_SEQ[1..0].clrn      = /RESET;

PROC_SEQ[0].d   =  PROC_SEQ_RD & PROC_SEQ[0].q
                 # PROC_SEQ[1].q & PROC_SEQ[0].q
                 # !PROC_SEQ_RD & !PROC_SEQ[0].q;

PROC_SEQ[1].d   =   PROC_SEQ[1].q
                 # !PROC_SEQ_RD & PROC_SEQ[0].q;

SEMIFOR_STFF.clrn = /RESET;
SEMIFOR_STFF.prn  = VCC;
SEMIFOR_STFF.clk  = PROC_SEQ_RD;
SEMIFOR_STFF.d    = VCC;

/SEMIFOR_ST       = SEMIFOR_STFF.q & PROC_SEQ_RD;

PROC_EN =   EN800_8FF & !A[7] & A[6] & A[5] & A[4] & !A[3] & !A[2]
         & !A[1] & A[0];

PROC_EN_WR    = PROC_EN & !/XIOW;

PROC_A1.prn       = /RESET;
PROC_A1.clk       = !PROC_EN_WR;
PROC_A1.clrn      = VCC;
PROC_A1.d         = ((PROC_EN & XD[0])
		  # (PROC_EN & !XD[3] & !XD[2] & !XD[1] & !XD[0]));

PROC_B1.prn       = /RESET;
PROC_B1.clk       = !PROC_EN_WR;
PROC_B1.clrn      = VCC;
PROC_B1.d         = ((PROC_EN & XD[0])
		  # (PROC_EN & !XD[3] & !XD[2] & !XD[1] & !XD[0]));

 PROC_A2.prn       = /RESET;
 PROC_A2.clk       = !PROC_EN_WR;
 PROC_A2.clrn      = VCC;
 PROC_A2.d         = ((PROC_EN & XD[0])
		   # (PROC_EN & !XD[3] & !XD[2] & !XD[1] & !XD[0]));

 PROC_B2.prn       = /RESET;
 PROC_B2.clk       = !PROC_EN_WR;
 PROC_B2.clrn      = VCC;
 PROC_B2.d         = ((PROC_EN & XD[0])
		   # (PROC_EN & !XD[3] & !XD[2] & !XD[1] & !XD[0]));

/PROC_A1_DIS       =  PROC_A1.q & /RESET;

/PROC_B1_DIS       =  PROC_B1.q & /RESET;

/PROC_A2_DIS       =  PROC_A2.q & /RESET;

/PROC_B2_DIS       =  PROC_B2.q & /RESET;

STARTCNTR1.d    =  /RESET;

STARTCNTR1.clk  = !(PROC_EN_WR & !XD[3] & !XD[2] & !XD[1] & !XD[0] & 
/RESET);

STARTCNTR1.clrn = !(CNTRRST[9].q & CNTRRST[8].q
		& CNTRRST[7].q & CNTRRST[6].q & CNTRRST[5].q
		& CNTRRST[4].q & CNTRRST[3].q & CNTRRST[2].q
		& CNTRRST[1].q & CNTRRST[0].q);

CNTRRST[].clk   = PWR_MNG_CLK;

CNTRRST[].clrn = !((PROC_EN_WR & !XD[3] & !XD[2] & !XD[1] & !XD[0]
		 & /RESET)
	       # (CNTRRST[9].q & CNTRRST[8].q & CNTRRST[7].q
		 & CNTRRST[6].q & CNTRRST[5].q & CNTRRST[4].q
		 & CNTRRST[3].q & CNTRRST[2].q & CNTRRST[1].q
		 & CNTRRST[0].q));

if STARTCNTR1.q  then			% Count while STARTCNTR1 %

	CNTRRST[].d = CNTRRST[].q + 1;

   else CNTRRST[].d = CNTRRST[].q;

end if;

EXTRST.oe  =  STARTCNTR1.q;
EXTRST.in  = !STARTCNTR1.q;

/EXTHRST   =  EXTRST.out;

CMDSTATE_FF.prn  = VCC;
CMDSTATE_FF.clk  = ISA_CLK;
CMDSTATE_FF.clrn = /RESET;
CMDSTATE_FF.d    = /CMDSTATE;

RSVD_INFF.prn    = VCC;
RSVD_INFF.clk    = ISA_CLK;
RSVD_INFF.clrn   = /RESET;
RSVD_INFF.d      = RSVD_IN;

IRQ1SIO_EN0      = !(/KYBD_CS & /RESET);
IRQ1SIO_EN1      = !(/XIOR & /RESET);

IRQ1SIO_RST      = !(IRQ1SIO_EN0 & IRQ1SIO_EN1);

IRQ1SIO_FF.prn   = VCC;
IRQ1SIO_FF.clk   = IRQ1;
IRQ1SIO_FF.clrn  = IRQ1SIO_RST;
IRQ1SIO_FF.d     = VCC;

IRQ1SIO          =  IRQ1SIO_FF.q;

RUN   =  !(HALT1 & HALT2);

PSWD1_PRTCTFF.s        = EN800_8FF & !A[7] & !A[6] & !A[5] & A[4]
                         & !A[3] & !A[2] & !A[1] & !A[0];
PSWD1_PRTCTFF.r        = GND;
PSWD1_PRTCTFF.clk      = GLOBAL(/XIOW);
PSWD1_PRTCTFF.clrn     = /RESET;

PSWD2_PRTCTFF.s         =  EN800_8FF & !A[7] & !A[6] & !A[5] & A[4]
                         & !A[3] & !A[2] & A[1] & !A[0];
PSWD2_PRTCTFF.r         = GND;
PSWD2_PRTCTFF.clk       = GLOBAL(/XIOW);
PSWD2_PRTCTFF.clrn      = /RESET;

CTL_REG0_EN              = EN800_8FF & !A[7] & !A[6] & !A[5] & A[4]
                          & A[3] & A[2] & !A[1] & !A[0];

CTL_REG0[7..0].s = CTL_REG0_EN &  XD[7..0];
CTL_REG0[7..0].r = CTL_REG0_EN & !XD[7..0];
CTL_REG0[].clk   =  /XIOW;
CTL_REG0[].clrn  = /RESET;

/ECPA          = !(CTL_REG0[2] & !CTL_REG0[1] & !CTL_REG0[0]);
/ECPB          = !(CTL_REG0[2] & !CTL_REG0[1] & CTL_REG0[0]);
/ECPC          = !(CTL_REG0[2] & CTL_REG0[1] & !CTL_REG0[0]);
/ECPD          = !(CTL_REG0[2] & CTL_REG0[1] & CTL_REG0[0]);
/MOTOR_EN      = CTL_REG0[3].q;

/L2_FLUSH      = CTL_REG0[4].q;
/L2_CACHE_DIS  = CTL_REG0[6].q & RUN;
/L2_CACHE_INH  = CTL_REG0[7].q;

	%*******************************************************%
	% Write Power Control Register 1 I/O address: 082A      %
	%                                                       %
	% (MSB)         Bits 7-5        Reserved                %
	%               Bit  4          I/O Strobe Key  (W/O)   %
	%               Bits 3-1        Data/Command            %
	%               B[3..1] to 83C750               (W/O)   %
	% (LSB)         Bit  0          83C750 D0       (R/W)   %
	%*******************************************************%

83CX_CS       = EN800_8FF & !A[7] & !A[6] &  A[5] & !A[4]
               & A[3] &!A[2] & A[1];

PWR_REG1_EN     = 83CX_CS & !A[0];

RWD0_BUFF.oe    = PWR_REG1_EN & !/XIOW & !XD[0];
RWD0_BUFF.in    = GND;

RWD0          = RWD0_BUFF.OUT;

/IO_STROBE  = !(XD[4] & PWR_REG1_EN & !/XIOW & PROC_RDY 
	     & !83CX_RESET);

	%******************************************************%
	% Write Power Control Register 2 I/O address: 082B     %
	%                                                      %
	% (LSB)         Bit  0          Reset 83C750 (W/O)     %
	%******************************************************%

PWR_REG2_EN     = 83CX_CS & A[0];

PWR_REG2.s      =  XD[0] & PWR_REG2_EN & /XIOW;
PWR_REG2.r      = !XD[0] & PWR_REG2_EN & /XIOW;
PWR_REG2.clrn   = VCC;
PWR_REG2.clk    = GLOBAL(/XIOW);

83CX_RESET      = PWR_REG2.q;

/ACTIVITY       = /FREEZE # !(IRQ1 # IRQ12);

/SUSREQ  =  VCC;

IDE_REG_EN      = !A[7] & !A[6] & A[5] & A[4] & A[3] & !A[2]
                  & !A[1] & !A[0] & EN800_8FF;

IDE_REG[0].d    = VCC;
IDE_REG[0].clk  = IDEIRQP;
IDE_REG[0].clrn = !(!XD[0] & IDE_REG_EN & !/XIOW # !/RESET);
IDE_REG[0].prn  = VCC;

/PLANAR_ID_RD   = !(EN800_8FF & !A[7] & A[6] & !A[5] & A[4]
                  & !A[3] & !A[2] & A[1] & !A[0] & !/XIOR);

/FREEZE.prn    =  /UNFREEZE & /RESET;
/FREEZE.clrn   =  VCC;
/FREEZE.d      =  GND;
/FREEZE.clk    =  !/SUSACK;

CLKFF_WR    = !A[7] & A[6] & A[5] & !A[4] & !A[3] & !A[2] & !A[0]
	     & EN800_8FF & !/XIOW;
CLKFF_SELL  = !A[7] & A[6] & A[5] & !A[4] & !A[3] & !A[2] & !A[1]
	     & !A[0] & EN800_8FF;
CLKFF_SELH   = !A[7] & A[6] & A[5] & !A[4] & !A[3] & !A[2] & A[1]
	      & !A[0] & EN800_8FF;

CLKFF[12..0].prn         = /RESET;
CLKFF[12..0].clrn        = VCC;

CLKFF[12..0].ena         = START_SHIFTFF.q # CLKFF_WR;
CLKFF[12..0].clk         = PWR_MNG_CLK;

if  START_SHIFTFF.q  then                  % Shift with wraparound %

	CLKFF[11..0].d   = CLKFF[12..1].q;
	CLKFF[12].d      = CLKFF[0].q;

	else if CLKFF_SELL then            % Write to CLKFF[7..0]  %

		CLKFF[1..0].d    = XD[1..0];
		CLKFF[2].d       = VCC;
		CLKFF[7..3].d    = XD[7..3];
		CLKFF[12..8].d   = CLKFF[12..8].q;

		else if CLKFF_SELH then     % Write to CLKFF[12..8]%

			CLKFF[7..0].d    = CLKFF[7..0].q;
			CLKFF[11..8].d   = XD[3..0];
			CLKFF[12].d      = VCC;

			else	CLKFF[12..0].d   = CLKFF[12..0].q;

		end if;

	end if;

end if;

SHIFT_ENFF.s    = CLKFF_SELH;           % Start shifting upon   %
                                        % write to 862  %
SHIFT_ENFF.r    = GND;
SHIFT_ENFF.prn  = /RESET;
SHIFT_ENFF.clrn = !GEN_STOP_BIT;        % Clear when it   %
                                                % reaches 15     %
SHIFT_ENFF.clk  = /XIOW;

SNC_SHIFT_ENFF.d        = SHIFT_ENFF.q; % One clock after%
                                                % SHIFT_ENFF    %
SNC_SHIFT_ENFF.ena      = /RESET;
SNC_SHIFT_ENFF.clrn     = /RESET;
SNC_SHIFT_ENFF.clk      = PWR_MNG_CLK;

CNTR[].clk              = PWR_MNG_CLK;
CNTR[].clrn             = /RESET;       % Counter resets to ZERO %

if SNC_SHIFT_ENFF.q  then    % Count while SNC_SHIFT_ENFF%

	CNTR[].d        = CNTR[].q + 1;
	else
		CNTR[].d        = CNTR[].q;

end if;

GEN_START_BIT   = !CNTR[3].q & !CNTR[2].q & !CNTR[1].q & CNTR[0].q;
GEN_STOP_BIT    =  CNTR[3].q &  CNTR[2].q &  CNTR[1].q & CNTR[0].q;
STOP_SHIFT      =  CNTR[3].q &  CNTR[2].q &  CNTR[1].q & !CNTR[0].q;

START_SHIFTFF.s         = GEN_START_BIT;
START_SHIFTFF.r         = STOP_SHIFT;
START_SHIFTFF.clrn      = /RESET;
START_SHIFTFF.clk       = PWR_MNG_CLK;

FRZ_DATA    = !CNTR[3].q & !CNTR[2].q & !CNTR[1].q & !CNTR[0].q
	    #  CNTR[3].q &  CNTR[2].q &  CNTR[1].q & !CNTR[0].q
	    #  CNTR[3].q &  CNTR[2].q &  CNTR[1].q &  CNTR[0].q
	    #  START_SHIFTFF.q & CLKFF[0].q;

RSVD_BIDI1 = TRI(DATA0, GND);
DATA0  = GND;

	%*******************************************************%
	%		    XD BUS 			%
	%*******************************************************%

XD_TRI_OE =  ((LIGHT_EN # CTL_REG0_EN # IDE_REG_EN # PROC_EN
          # SER_EN # CLKFF_SELL # CLKFF_SELH) & !/XIOR)
          # PROC_SEQ_RD;

XD[0]  = TRI(D[0], XD_TRI_OE);

D[0]   = CTL_REG0_EN & CTL_REG0[0].q
       # LIGHT_EN & HDD_LEDFF.q
       # PROC_SEQ[0].q & PROC_SEQ_RD
       # PROC_A1.q & PROC_EN
       # IDE_REG[0].q & IDE_REG_EN
       # SER_REG[0].q & SER_EN;

XD[1]  = TRI(D[1], XD_TRI_OE);
D[1]   = CTL_REG0_EN & CTL_REG0[1].q
       # PROC_SEQ[1].q & PROC_SEQ_RD
       # PROC_B1.q & PROC_EN
       # SER_REG[1].q & SER_EN;

XD[2] = TRI(D[2], XD_TRI_OE);
D[2]  = CTL_REG0_EN & CTL_REG0[2].q # PROC_A2.q & PROC_EN;

XD[3] = TRI(D[3], XD_TRI_OE);
D[3]  = CTL_REG0_EN & CTL_REG0[3].q # PROC_B2.q & PROC_EN;

XD[4] = TRI(D[4], XD_TRI_OE);
D[4]  = CTL_REG0_EN & CTL_REG0[4].q # SER_EN & SER_REG[2].q;

XD[5] = TRI(D[5], XD_TRI_OE);
D[5]  = CTL_REG0_EN & CTL_REG0[5].q # SER_EN & PC1_DATA;

XD[6] = TRI(D[6], XD_TRI_OE);
D[6]  = CTL_REG0_EN & CTL_REG0[6].q # PROC_EN & RSVD_INFF.q
      # SER_EN & PC2_DATA;

XD[7] = TRI(D[7], XD_TRI_OE);
D[7]  = CTL_REG0_EN & CTL_REG0[7].q # PROC_EN & CMDSTATE_FF.q
      # SER_EN & L2_DATA;

END;

1.5 EPLD Pinout

PIN#

SIGNAL NAME

TYPE

1

FD_MTR_EN#

O

2

RUN

O

3

L2_WT#

O

4

EXTHRST#

I

5

IDEIRQP(RESERVED)

I

6

PROC2_PD_RD#

O

7

PROC1_PD_RD#

O

8

CACHE_PD_RD#

O

9

XIOR#

I

10

CMD_STATE(RESERVED)#

I

11

RESET#

I

12

GND

13

GND

14

IRQ1

I

15

IRQ12

I

16

XIOW#

I

17

SUSACK(RESERVED)#

I

18

VCC

19

VCC

20

PWR_MNG_CLK

I

21

ECS[0]

I

22

ECS[1]

I

23

RTC_AS1#

O

24

RTC_AS0#

O

25

RD_3F3#

O

26

ISA_CLK

I

27

HALT1

I

28

HALT2

I

29

SER_CLKEN

O

30

ACTIVITY(RESERVED)#

O

31

RTC_WR#

O

32

RTC_RD#

O

33

PLANAR_ID_RD#

O

34

NVRAM_WR#

O

35

PROC_A1_DIS#

O

36

PROC_B1_DIS#

O

PIN#

SIGNAL NAME

TYPE

37

GND

38

GND

39

PROC_A2_DIS#

O

40

PROC_B2_DIS#

O

41

RSVD_IN

I

42

RSVD_BIDI1

I/O

43

VCC

44

VCC

45

ROM_EN#

O

46

SEMIFOR_ST#

O

47

UNFREEZE(RESERVED)#

I

48

RWD0(RESERVED)

I/O(t.s)

49

FRZ_DATA

O

50

PROC_RDY(RESERVED)

I

51

L2_FLUSH#

O

52

KYBD_CS#

53

L2_DATA

I/O

54

PC2_DATA

I/O

55

PC1_DATA

I/O

56

IRQ1SIO

O

57

RTC_ALE#

O

58

HFCS1(RESERVED)#

O

59

ECS[2]

I

60

ECSEN#

I

61

XA[7]

I

62

GND

63

GND

64

XA[6]

I

65

XA[5]

I

66

XA[4]

I

67

XA[3]

I

68

VCC

69

VCC

70

XA[2]

I

71

XA[1]

I

72

XA[0]

I

PIN#

SIGNAL NAME

TYPE

73

XD[7]

I/O

74

XD[2]

I/O

75

NVRAM_RD#

O

76

L2_CACHE_INH#

O

77

HFCS0(RESERVED)#

O

78

SER_CLK

O

79

EQP_PR_RD#

O

80

SUSREQ(RESERVED)#

O

81

L2_CACHE_DIS#

O

82

L2_CACHE_DCD#

O

83

HDD_LED#

O

84

ECPD#

O

85

ECPC#

O

86

ECPB#

O

PIN#

SIGNAL NAME

TYPE

87

GND

88

GND

89

ECPA#

O

90

DRAM_PD_RD#

O

91

83CX_RESET(RESERVED)

I

92

XD[6]

I/O

93

VCC

94

VCC

95

XD[5]

I/O

96

XD[4]

I/O

97

XD[3]

I/O

98

XD[1]

I/O

99

XD[0]

I/O

100

IO_STROBE(RESERVED)#

O