A well written application note entitled "Pcnet Family Board Design and Layout Recommendations" is also available from AMD. Some of the design practices mentioned in this section are described more fully in the application note.
An 8-pin socketed serial EEPROM is used to automatically configure the controller at power up, and a green LED is used to display the link status. The reference design does not support writing to the serial EEPROM.
The Ethernet controller offers some additional capabilities that are not implemented in the reference design. Among these are 10BASE-2 and other protocol implementations which require the use of the Attachment Unit Interface (AUI). The Ethernet controller contains a General Purpose Serial Interface (GPSI) which is not used. The expansion ROM interface is also not used.
The combination of analog and digital circuitry in the Ethernet interface poses significant challenges for the circuit, system, and physical designer. Low noise design techniques are required to ensure proper function of the interface.
Refer to Section for register listings and setup information.
Noise-free power and ground connections are critical for good performance of the Ethernet implementation. Using a circuit board with four or more layers with dedicated power and ground planes can make designing a reliable Ethernet interface easier.
Adequate decoupling is necessary for all designs. The reference design uses a bulk capacitor for low-frequency decoupling (33uF) and 9 high-frequency decoupling capacitors (0.1uF) which are arranged around the perimeter of the device. The VCC and ground pins are connected directly to the high-frequency capacitors, rather than through the planes, so that inductance between the power and ground pins is minimized.
A 0.1uF capacitor is placed between the AVSS1 and AVDD3 pins, and a low-pass filter is placed between pins AVSS2 and AVDD2. In addition to the 10uF capacitor used in this filter, the 79C970A application note suggests a 0.1uF capacitor be placed in parallel with the 10uF.
1.1.1.2 Ethernet 10BASE-T Layout Guidelines
Since common mode noise is the primary source of radiated energy from this interface it is suggested that a common-mode choke be used. This reference design uses a filter/transformer with an integrated common-mode choke for this purpose.
1.1.1.3 Ethernet Oscillator Guidelines
Please refer to the 79C970A specification and the application note described at the start of the Ethernet section to be sure that your crystal oscillator will meet the controller requirements.
An output from the Ethernet controller (LNKST*) is also wired to the power management controller socket. This signal is intended to allow a power management controller the ability to wake up the system when there is Ethernet activity.
The 53C810 supports the following features:
Refer to Section for register listings and setup information.
1.2.1.1 SCSI Component Location
The PCI and SCSI buses each have requirements which must be satisfied to ensure proper function of each bus. In the reference design, the SCSI controller is located close to the PCI bus to minimize trace length, and it is oriented so that critical path lengths for PCI and SCSI buses are minimized, and so that signal crossovers are avoided.
1.2.1.2 SCSI Bus Routing
The wiring guidelines section of this document describe the general rules to use in routing the SCSI bus. The goal is to provide wiring channels which are low noise and not subject to crosstalk with other signals.
1.2.1.3 SCSI Decoupling
The specification for the 53C810 indicates that bypass capacitor values between .01 and .1uF should provide adequate noise isolation. This reference design used a single bulk decoupling capacitor of value 33uF and about (10) .01uF capacitors located on the back side of the system board, around the perimeter of the device.
1.2.1.4 SCSI Impedance Matching
The SCSI-3 SPI specification requires characteristic SCSI bus impedance to be 84 "12 ohms. The characteristic impedance of multilayer PC cards can vary, but the internal planes will often be found to be on the lower end of this range. Internal traces for this reference design have an approximate impedance of 75 ohms while external traces have an impedance of 85-95 ohms. This means that any combination of wiring on internal and external layers was acceptable. Traces that run on outer planes have higher impedances than those that run on inner planes.
1.2.1.5 SCSI EMC Considerations
The reference design includes a set of inductors at the internal SCSI connector, which are intended to limit EMI radiated by the internal (flat) SCSI cable. The external SCSI connector was not so equipped because the shield of the external SCSI cable is considered adequate to limit the radiated EMI to acceptable limits.
Figure 1 shows a block diagram of the reference design SCSI bus implementation. The design requires at least one SCSI device to be installed on the SCSI bus via J32, the internal SCSI connector. The internal SCSI bus must be terminated off-board, at the SCSI device at the end of the cable. There must be exactly one terminator on the internal SCSI cable. The internal SCSI connector provides fused external terminator power on pin 26.
When a SCSI cable with a compliant SCSI device is plugged into the external SCSI connector (J19), pin 36 of the connector is shorted to ground. This causes the EXT_SCSI_GND24 signal to go low. This causes the active (to 2.9v) terminator located by the external SCSI connector to be disabled. This mechanism enables the onboard terminator while no devices are connected to the external SCSI connector, and it disables the onboard terminator while an external SCSI device is attached.
If an external SCSI device is attached, it is necessary to terminate the last device on the cable in accordance with normal SCSI practice. However, if no SCSI devices are attached to the external SCSI connector, it is not necessary to install a terminator in the connector.
It is still necessary to use a terminator on the last external drive to terminate the SCSI bus on the external side. The external SCSI connector provides fused external terminator power on pin 38.
Warning: The general purpose control register (GPCNTL 47/C7) bits 0:1 (little endian) must remain in their default settings (1's) so that GPIO bits 0:1 are configured as inputs. Changing this setting can result in damage to the hardware.
This reference design routes the signal IRQ# from the SCSI controller to several locations including the MPIC, the ISA bridge, and the power management controller socket. This is done to allow the greatest degree of flexibility in handling the interrupt under various operating systems. It is expected that only the interrupt wired to the MPIC will be used, as this is the most efficient way to service SCSI interrupts. The interrupt which is routed to MPIC is level sensitive, and can be treated like any other level sensitive interrupt except as noted in the above paragraph.
Refer to the schematics and to the SuperI/O data sheet for more information. Refer to Section for Register list, configuration, and Setup information.
Conventional (Timer 2) PC speaker functions are also provided (both the Timer 2 signal from the SIO, and the audio chip, drive the speaker).
The system provides for stereo capture and playback. It can play MIDI files, but it is not a full-functioned MIDI system. It has separate DMA channels for record and playback. The system is processor driven and does not include a DSP. Compression and decompression are supported in the hardware. The audio output is to a single speaker mounted in the cabinet. Also supported are four rear-mounted 3.5 mm jacks for:
Refer to Section for configuration, setup and initialization information.
| Table 1. Business Audio Subsystem Performance
|
|
| Sampling Rate
|
48 KHz per Channel Maximum
|
| Channel Bandwidth (Line Out and Headphone)
|
20 Hz to 20 KHz (+1/-3dB)
|
| Dynamic Range
|
16-bit Resolution
|
| Line In Signal to Noise + Distortion Ratio
|
80 dB Min @ 1KHz (Measured at Line Out)
|
| Microphone Signal to Noise + Distortion Ratio
|
60 dB Min @ 1KHz (Measured at Line Out)
|
| Table 2. Business Audio Connector Specifications
|
|
| Line In
|
|
| Input Impedance
|
4 Kohms (use 2 Kohms source impedance or lower)
|
| Signal Level
|
2 v rms Nominal
|
|
|
|
| Microphone Input
|
|
| Input Impedance
|
3.8 Kohms (use 50 to 1000 ohm microphone)
|
| Phantom Power
|
Stereo 0.5ma for Nominal Operation at 2 v DC
|
| Signal Level
|
10 mv rms Nominal, 50 mv rms Maximum
|
|
|
|
| CD ROM Input (Internal)
|
|
| Input Impedance
|
3 Kohms
|
| Signal Level
|
1 v rms Nominal
|
|
|
|
| Line Out
|
|
| Output Impedance
|
1 Kohm (use 10K ohm Load Impedance or Higher)
|
| Signal Level
|
2 v rms Nominal
|
|
|
|
| Headphone Output
|
|
| Output Impedance
|
12 ohms
|
| Signal Level
|
1.5 v rms Nominal
|
|
|
|
| System Speaker Output
|
|
| Output Impedance
|
8 ohms Typical
|
| Power Output
|
1 Watt Maximum at 8 ohms
|
|
|
|
| Fax/Modem Connection (Internal)
|
|
| Input Impedance
|
4 Kohms (use 2 Kohms source impedance or lower)
|
| Signal Level (Input)
|
2 v rms Nominal
|
| Output Impedance
|
12 ohms
|
| Signal Level (Output)
|
1.5 v rms Nominal
|
| Input Impedance (Microphone)
|
3.8 Kohms (use 50 to 1000 ohm microphone)
|
| Signal Level (Microphone Input)
|
10 mv rms Nominal, 50 mv rms Maximum
|
| ISA Port 0534
|
Read/Write
|
Reset to 40h
|
Bit 0 Initialization. This bit is set when the module is in a state which cannot respond to parallel bus cycles. This bit is read only.
Bit 1 Mode Change Enable. This bit must be set whenever the current functional mode of the module is changed. Specifically, the Clock and Data Format and Interface Configuration registers cannot be changed unless this bit is set. MCE should be cleared at the completion of the desired register changes.
Bit 2 Transfer Request Disable. This bit, when set, causes DMA transfers to cease when the Interrupt Status (INT) bit of the Status Register is set.
Bit 3 Reserved
Bits 7:4 Index Address. These bits define the address of the register accessed by the Indexed Data Register.
Immediately after reset and once the module has left the INIT state, the initial value of this register will be 40h. During initialization, this register cannot be written and is always read 80h.
1.4.3.2 Audio Indexed Data Register
| ISA Port 0535
|
Read Only
|
Reset n/a
|
Bits 7:0 Indexed Register Data. These bits contain the contents of the register referenced by the Indexed Data Register.
During initialization, this register cannot be written and is always read as 80h.
| ISA Port 0536
|
Read Only
|
Reset to 40h
|
Bit 0 Capture Upper/Lower Byte. This bit indicates whether the PIO capture data
ready is for the upper or lower byte of the channel. This bit is read only.
0 = Lower byte ready.
1 = Upper byte ready or any 8 bit mode.
Bit 1 Capture Left/Right Sample. This bit indicates whether the PIO capture data
waiting is for the right channel or left channel. This bit is read only.
0 = Right channel.
1 = Left channel or mono.
Bit 2 Capture Data Ready. The PIO Capture Data Register contains data ready for
reading by the host. This bit should only be used when direct programmed
I/O data transfers are desired. This bit is read only.
0 = Data is stale. Do not reread.
1 = Data is fresh. Ready for next host data read.
Bit 3 Sample Over/Underrun. This bit indicates that the most recent sample was not serviced in time and therefore either a Capture Overrun or Playback Underrun has occurred. If both capture and playback are enabled, the source which set this bit can be determined by reading the Playback Underrun and Capture Overrun bits in the Test and Initialization Register.
Bit 4 Playback Upper/Lower Byte. This bit indicates whether the PIO playback
data needed is for the upper or lower byte of the channel. This bit is read only.
0 = Lower byte needed.
1 = Upper byte needed or any 8 bit mode.
Bit 5 Playback Left/Right Sample. This bit indicates whether the PIO playback
data needed is for the right channel DAC or left channel DAC. This bit is read
only.
0 = Right channel needed.
1 = Left channel or mono.
Bit 6 Playback Data Register Ready. The PIO Playback Data Register is ready for
more data. This bit should only be used when direct programmed I/O data
transfers are desired. This bit is read only.
0 = DAC data is still valid. Do not overwrite.
1 = DAC data is stale. Ready for next host data write value.
Bit 7 Interrupt Status. This sticky bit (the only one) indicates the status of the
interrupt logic. This bit is cleared by any host write of any value to this register.
The Interrupt Enable bit of the Pin Control Register determines whether the
state of this bit is reflected on the Interrupt Pin of the AD1848. The only
interrupt condition supported by the AD1848 is generated by the underflow
of the DMA Current Count Register.
0 = Interrupt pin inactive.
1 = Interrupt pin active.
| ISA Port 0537
|
Read/Write
|
Reset n/a
|
Bits 7:0 PIO Capture Data Register. This is the control register where capture data is read during programmed I/O data transfers.
The reading of this register will increment the state machine so that the following read will be from the next appropriate byte in the sample. The exact byte which is next to be read can be determined by reading the Status Register. Once all relevant bytes have been read, the state machine will stay pointed to the last byte of the sample until a new sample is received. Once this has occurred, the state machine and status register will point to the first byte of the sample. Until a new sample is received, reads from this register will return the most significant byte of the sample.
Bits 7:0 PIO Playback Data Register. This is the control register where playback data is written during programmed I/O data transfers.
Writing data to this register will increment the playback byte tracking state machine so that the following write will be to the correct byte of the sample. Once all bytes of a sample have been written, subsequent byte writes to this port are ignored.
Bits 1:0 Joystick Rate Control. Selects the operating speed of the joystick.
00 = Slowest speed.
01 = Medium speed.
10 = Medium fast speed.
11 = Fastest speed.
Bit 2 RESERVED.
Bit 4:3 SoundBlaster ADPCM Mode. Selects the SoundBlaster ADPCM playback.
00 = Silence is output (i.e., mute) during SoundBlaster ADPCM playback.
01 = Silent is played for SoundBlaster 3:1 and 4:1 ADPCM. The cs4231 ADPCM is used for 2:1.
10 = An interrupt is generated when SB ADPCM is detected. (see CS4232
configuration for how to assign interrupt level.)
11 = RESERVED.
Bit 5 Control host interrupt generation when a context switch occurs.
0 = No interrupt on context switch.
1 = CS4232 interrupt generated on context switch.
Bit 7:6 Power Management control for CS4232.
00 = All functions active
01 = Codec digital logic powered down. Some register values destroyed
10 = Sound Blaster and MPU-401 functions powered down. All Plug and Play
configuration is retained.
11 = Full chip power down. Same as power on reset.
Bit 0 This bit is used to generate the clock for the Plug and Play EEPROM.
Bit 1 This bit is used to output serial data to the Plug and Play EEPROM.
Bit 2 This bit is used to read serial data from the Plug and Play EEPROM and to
enable the CLK and DOUT onto the CS4232 pins.
0 = EEPROM interface disabled.
1 = EEPROM interface enabled.
Bit 3 RESERVED.
Bit 5:4 These two bits are used to control an additional A/D mux and enable for an
analog loopback path.
00 = EEPROM interface enabled.
01 = Codec Input mux is mixed into output mixer. A/D input is from the input
mix.
10 = Codec Input mux is mixed into output mixer. A/D input is from line out
puts.
11 = RESERVED.
Bit 7:6 RESERVED.
Bit 0 Joystick A Control X.
Bit 1 Joystick A Control Y.
Bit 2 Joystick B Control X.
Bit 3 Joystick B Control Y.
Bit 4 Joystick A Button 1.
Bit 5 Joystick A Button 2.
Bit 6 Joystick B Button 1.
Bit 7 Joystick B Button 2.
The joystick consist of one register. Write to it to set the one-shots. Then read at intervals to see how long they take to reset. The buttons can be read at any time. The address of the joystick port is set during the configuration of the CS4232 (see CS4232 configuration).
| Table 3. SoundBlaster Addresses
|
|
| Address
|
Description
|
| 00 - 03
|
Left/Right FM registers. These registers are inside the OPL3. See the OPL3 spec for
their function.
|
| 04
|
Mixer Index register
|
| 05
|
Mixer Data register
|
| 06
|
Reset (write only). setting D[0] (little endian) to 1 and then to 0 resets the Sound Blast
er logic
|
| 0A
|
Read Data Port (read only). When D[7] (little endian) is set = 1, then valid data is
available in this register. the data may be the result of a Command that was previously
written to the Command/Write register or audio data.
|
| 0C
|
Command/Write Data (write only). The command/write data register is used to send
the Sound Blaster commands to the CS4232.
|
| 0C
|
Write Buffer Status (read only). The write buffer status register bit D[7] (little endian)
indicates when the CS4232 is ready to accept another command to the command/Write
Data register. D[7]= 1 indicates ready. D[7]=0 indicates not ready.
|
| Mixer Registers (Little Endian)
|
||||||||
| Register
|
D7
|
D6
|
D5
|
D4
|
D3
|
D2
|
D1
|
D0
|
| 00h
|
Data Reset
|
|||||||
| 04h
|
Reserved
|
|||||||
| 04h
|
Volume Left
|
Volume Right
|
||||||
| 06h
|
Reserved
|
|||||||
| 08h
|
Reserved
|
|||||||
| 0Ah
|
X
|
X
|
X
|
X
|
X
|
X
|
Mic Mix
|
|
| 0Ch
|
X
|
X
|
Input Filter
|
Input Select
|
X
|
|||
| 0Eh
|
X
|
X
|
DNF1
|
X
|
X
|
X
|
VSTC
|
X
|
| 20h
|
Reserved
|
|||||||
| 22H
|
Master Volume Left
|
Master Volume Right
|
||||||
| 24h
|
Reserved
|
|||||||
| 26h
|
FM Volume Left
|
FM Volume Right
|
||||||
| 28h
|
CD Volume Right
|
CD Volume Right
|
||||||
| 2Ah
|
Reserved
|
|||||||
| 2Ch
|
Reserved
|
|||||||
| 2Eh
|
Line Volume Right
|
Line Volume Right
|
||||||
Input Filter (Little Endian) |
|||
Filter |
D5 |
D4 |
D3 |
Low Filter |
0 |
x |
0 |
High Filter |
0 |
x |
1 |
No Filter |
1 |
x |
x |
| Input Select
|
||
| Input
|
B2
|
B1
|
| Microphone
|
x
|
0
|
| CD Audio
|
0
|
1
|
| Line-In
|
1
|
1
|
The MPU-401 interface consist of two registers that are mapped into the PC I/O address space. The address is determined by the configuration ( see CS4232 configuration). The standard address for MIDI Transmit/Receive is port 330h. Port 331h is usually used for the Command/Status port.
| Address + Base
|
Description
|
| 0 (Read)
|
Receive Port
|
| 0 (Write)
|
Transmit Port
|
| 1 (Read)
|
Status Port
|
| 1 (write)
|
Command Port
|
1.4.11.1 MIDI Status Register
Bits 5:0 These bits are the data of the last command written
0 = EEPROM interface disabled.
1 = EEPROM interface enabled.
Bit 6 CXS-Transmit buffer status flag.
0 = not full.
1 = full, wait.
Bit 7 RXS-Receive buffer status flag.
0 = not empty.
1 = empty, wait. .
When an interrupt is generated by the MPU-401, it is cleared in the CS4232 by a read of the MIDI Receive Port. This is the same port as the Base address for this logical device set in the configuration (see CS4232 configuration).
