Section 1
Registers and System Setup

1.1 CPU Initialization

All memory pages 2G to 4G must be marked as non-cacheable.

The segment register T bit (bit 0) defaults to 0, which is the normal storage access mode. It must be left in this state for the hardware to function. Direct store (PIO) segments are not supported.

Set the bit that controls ARTRY# negation, HID0[7], to 0 to enable the precharge of ARTRY#. It may be necessary set HID0[7] to 1 to disable the precharge of ARTRY# for reference design configurations having a CPU bus agent (such as an added L2) that drives the ARTRY# line. Software must set this bit before allowing any CPU bus traffic to which the CPU agent might respond. Note that PCI to memory transactions cause the 660 bridge to broadcast snoop operations on the CPU bus.

HID0 bit 0, Master Checkstop Enable, defaults to 1, which is the enabled state. Leave it in this state so that checkstops can occur.

Reference design errors are reported through the 660 bridge by way of the TEA# and MCP# pins. Because of this, the bus error checking in the CPU must be disabled by setting HID0 bits 2 and 3 to zero (in the 604 CPU, enable L1 cache parity checking by setting HID0 bit 1 to one).

1.1.1 Fast L2/Data Streaming Mode (No-DRTRY#)

In no-DRTRY# mode, each CPU card must also provide correct generation of DRTRY# for the CPU on the card. For the PowerPC 604 CPU card, wire DRTRY# of the CPU to #HRESET of the connector (rather than to connector DRTRY#). This will provide a low level on the CPU DRTRY# at reset and a high level under normal operation, which will place the 604 CPU in fast L2/data streaming mode.

1.2 660 Bridge Initialization

1 Read the SIMM presence detect and SIMM type registers.

2 Set up and check the memory-related registers in the 660 bridge (see the 660 Bridge User's Manual).

3 Program the timer in the ISA bridge register which controls ISA refresh timing. In SIO compatible bridges, it should be programmed to operate in Mode 2 with an interval of approximately 15 usec.

4 Make sure 200 usec has elapsed since starting the refresh timer so that sufficient refresh cycles have occurred to properly start the memory. This will be hidden if approximately 120 Flash accesses occur after the timer is started and before the memory initialization starts.

5 Initialize all of memory so that all parity bits are properly set. (The CPU may cache unnecessary data; hence, all of memory must be initialized.) The 660 bridge does not require reconfiguration when port 4Dh in the ISA bridge is utilized to reset the native I/O and the ISA slots.

1.2.1 CPU to PCI Configuration Transactions

The transfer size must match the capabilities of the target PCI device for configuration cycles. The reference design supports 1-, 2-, 3-, and 4-byte transfers that do not cross a 4-byte boundary.

Address unmunging and data byte swapping follows the same rules as for system memory with respect to BE and LE modes of operation. Address unmunging has no effect on the CPU address lines which correspond to the IDSEL inputs of the PCI devices.

Table 1. IDSEL Assignments
Device	ID Sel Line	60X Address*	PCI Address
82378ZB PCI to ISA Bridge	A/D 11	8080 08XXh	080 08XX
53C810 SCSI Controller	A/D 12	8080 10XXh	080 10XX
PCI Slot 1 (lower)	A/D 13	8080 20XXh	080 20XX
PCI Slot 2 (upper)	A/D 14	8080 40XXh	080 40XX
Multiprocessor Interrupt Controller	A/D 15	8080 80XXh	080 80XX
79C970 Ethernet Controller	A/D 16	8081 00XXh	081 00XX
Note: *This address is independent of contiguous I/O mode.

1.2.1.1 Preferred Method of Generating PCI Configuration Transactions

The preferred method for generating PCI configuration cycles is via the 660 Bridge indexed Bridge Control Registers (BCRs). This configuration method is described in Section 4 of the 660 User's Manual. The IDSEL assignment, address assignment, and the PCI_AD lines are shown here in Table 2.

1.2.1.2 650 Bridge Compatible Method

If it is not possible to use indexed BCRs to generate PCI configuration cycles, they can be generated by an alternate method known as the 650 bridge compatible method. CPU accesses to the address range 2G+8M to 2G+16M cause the bridge to arbitrate for the PCI bus and then to execute a type 0 PCI configuration transaction as described in the PowerPC Reference Platform Specification and implemented by the IBM27-82650 PowerPC to PCI Bridge. This is referred to as the 650 compatible configuration method. This method of accessing PCI configuration space does not allow access to the PCI configuration registers in the bridge chip. It should not be used unless required to maintain 650 compatibility.

When using the 650 bridge compatible configuration method, use only the specified address. Using other addresses can cause bus contention because multiple PCI slots could be selected. For example, using any CPU address in the range 8080 0000 to 80FF FFFF with both AD11 = 1 and AD12 = 1, causes selection of both the SIO and any device in slot 1, possibly resulting in damage.

1.2.2 PCI Configuration Scan

Software must use only the addresses specified. Using any addresses that causes more than one IDSEL to be asserted (high) can cause bus contention, because multiple PCI agents will be selected.

1.2.2.1 Multi-Function Adaptors

The 660 Bridge supports multi-function adapters. It passes the address of the load or store instruction that causes PCI configuration cycle unmodified (except that the three low-order bits are unmunged in little endian mode and the two low-order address bits are set to zero in either endian mode). Addresses, therefore, may be selected with non-zero CPU address bits (21:23)-corresponding to PCI bits (10:8)-to configure multi-function adaptors. For example, to configure device 3 in slot 1, use address 80C0 03XXh. To configure device 7 in slot 2, use address 8084 07XXh.

1.2.2.2 PCI to PCI Bridges

The 660 bridge supports both Type 0 and Type 1 configuration cycles.

1.2.3 660 Bridge Indexed BCR Summary

Table 2. 660 Bridge Indexed BCR Listing
Bridge Control Register	Index	R/W	Bytes	Set To1	Note
PCI Vendor ID	Index 00-01	R	2	-
PCI Device ID	Index 02-03	R	2	-
PCI Command	Index 04-05	R/W	2	-
PCI Device Status	Index 06-07	R/W	2	-
Revision ID	Index 08	R	1	-
PCI Standard Programming Interface	Index 09	R	1	-
PCI Subclass Code	Index 0A	R	1	-
PCI Class Code	Index 0B	R	1	-
PCI Cache Line Size	Index 0C	R	1	-
PCI Latency Timer	Index 0D	R	1	-
PCI Header Type	Index 0E	R	1	-
PCI Built-in Self-Test (BIST) Control	Index 0F	R	1	-
PCI Interrupt Line	Index 3C	R	1	-
PCI Interrupt Pin	Index 3D	R	1	-
PCI MIN_GNT	Index 3E	R	1	-
PCI MAX_LAT	Index 3F	R	1	-
PCI Bus Number	Index 40	R	1	-
PCI Subordinate Bus Number	Index 41	R	1	-
PCI Disconnect Counter	Index 42	R/W	1	-
PCI Special Cycle Address BCR	Index 44-45	R	2	-
Memory Bank 0 Starting Address	Index 80	R/W	1	Memory	2
Memory Bank 1 Starting Address	Index 81	R/W	1	Memory	2
Memory Bank 2 Starting Address	Index 82	R/W	1	Memory	2
Memory Bank 3 Starting Address	Index 83	R/W	1	Memory	2
Memory Bank 4 Starting Address	Index 84	R/W	1	Memory	2
Memory Bank 5 Starting Address	Index 85	R/W	1	Memory	2
Memory Bank 6 Starting Address	Index 86	R/W	1	Memory	2
Memory Bank 7 Starting Address	Index 87	R/W	1	Memory	2
Memory Bank 0 Ext Starting Address	Index 88	R/W	1	Memory	2
Memory Bank 1 Ext Starting Address	Index 89	R/W	1	Memory	2
Memory Bank 2 Ext Starting Address	Index 8A	R/W	1	Memory	2
Memory Bank 3 Ext Starting Address	Index 8B	R/W	1	Memory	2
Memory Bank 4 Ext Starting Address	Index 8C	R/W	1	Memory	2
Memory Bank 5 Ext Starting Address	Index 8D	R/W	1	Memory	2
Memory Bank 6 Ext Starting Address	Index 8E	R/W	1	Memory	2
Memory Bank 7 Ext Starting Address	Index 8F	R/W	1	Memory	2
Memory Bank 0 Ending Address	Index 90	R/W	1	Memory	2
Memory Bank 1 Ending Address	Index 91	R/W	1	Memory	2
Memory Bank 2 Ending Address	Index 92	R/W	1	Memory	2
Memory Bank 3 Ending Address	Index 93	R/W	1	Memory	2
Memory Bank 4 Ending Address	Index 94	R/W	1	Memory	2
Memory Bank 5 Ending Address	Index 95	R/W	1	Memory	2
Memory Bank 6 Ending Address	Index 96	R/W	1	Memory	2
Memory Bank 7 Ending Address	Index 97	R/W	1	Memory	2
Memory Bank 0 Ext Ending Address	Index 98	R/W	1	Memory	2
Memory Bank 1 Ext Ending Address	Index 99	R/W	1	Memory	2
Memory Bank 2 Ext Ending Address	Index 9A	R/W	1	Memory	2
Memory Bank 3 Ext Ending Address	Index 9B	R/W	1	Memory	2
Memory Bank 4 Ext Ending Address	Index 9C	R/W	1	Memory	2
Memory Bank 5 Ext Ending Address	Index 9D	R/W	1	Memory	2
Memory Bank 6 Ext Ending Address	Index 9E	R/W	1	Memory	2
Memory Bank 7 Ext Ending Address	Index 9F	R/W	1	Memory	2
Memory Bank Enable	Index A0	R/W	1	Memory	2
Memory Timing 1	Index A1	R/W	1	-	2
Memory Timing 2	Index A2	R/W	1	-	2
Memory Bank 0 & 1 Addressing Mode	Index A4	R/W	1	Mode 2	2
Memory Bank 2 & 3 Addressing Mode	Index A5	R/W	1	-
Memory Bank 4 & 5 Addressing Mode	Index A6	R/W	1	-
Memory Bank 6 & 7 Addressing Mode	Index A7	R/W	1	-
Cache Status	Index B1	R/W	1	-
Refresh Cycle Definition	Index B4	R	1	-
Refresh Timer B5 (Not used-see Indexed BCR D0)	Index B5	R	1	-
RAS Watchdog Timer	Index B6	R/W	1	-
PCI Bus Timer (Not used)	Index B7	R	1	-
Single-Bit Error Counter	Index B8	R/W	1	-
Single-Bit Error Trigger Level	Index B9	R/W	1	-
Bridge Options 1	Index BA	R/W	1	-
Bridge Options 2	Index BB	R/W	1	-
Error Enable 1	Index C0	R/W	1	-
Error Status 1	Index C1	R/W	1	-
Error Simulation 1	Index C2	R/W	1	-
CPU Bus Error Status	Index C3	R	1	-
Error Enable 2	Index C4	R/W	1	-
Error Status 2	Index C5	R/W	1	-
Error Simulation 2	Index C6	R/W	1	-
PCI Bus Error Status	Index C7	R/W	1	-
CPU/PCI Error Address	Index C8-CB	R/W	4	-
Single-Bit ECC Error Address	Index CC-CF	R/W	4	-
Refresh Timer Divisor	Index D0-D1	R/W	2	-
Suspend Refresh Timer	Index D2-D3	R/W	2	-
Bridge Chip Set Options 3	Index D4	R/W	1	-
Notes: In this column, a long dash - means that the initialization firmware does not write to this regis ter. The register is either not used or not written to, or the value of it depends on changing cir cumstances. If the word Memory appears, please refer to the System Memory section of the 660 User's Manual. The initialization firmware sets these registers depending on the information reported by the DRAM presence detect registers.

1.3 ISA Bridge (SIO) Initialization

The SIO chip should be configured prior to any other PCI bus agent. The SIO PCI arbiter is automatically enabled upon power-on reset. During power-on reset, the SIO drives the A/D(31:0), C/BE#(3:0), and par signals on the PCI bus.

The system I/O EPLD uses the decode circuits in the SIO that produce the signals ECSADDR[2:0] and UBUSCOE# to decode the motherboard register addresses. For this reason, utility bus A and B decode registers must be initialized as shown in Table 3.

The ISA clock divisor must be set as indicated prior to running any CPU to PCI transactions. If the configuration information is stored in Flash, this should pose no problem.

The SIO must be programmed so that interval timer 1 operates in mode 2 with a period of approximately 15 microseconds. This timer controls the ISA refresh interval. It must be programmed at least 200 microseconds before any access to ISA DRAM is attempted.

PCI memory write cycles destined for ISA can use a 32-bit posted write buffer in the SIO. Bit 2 of the PCI control register controls the enabling of the posted write buffer. The default (power-on reset) state for the posted write buffer is disabled. It is required that the posted write buffer be enabled.

Note that PCI burst transactions are not supported by the SIO. For burst transactions, the SIO will always target abort after the first data phase. The system will not allow the CPU to burst to the SIO (or any other PCI agent). No PCI master should be programmed to attempt burst transactions to the SIO.

The SIO defaults (after power-on reset) to the slow sampling point (bits 4:3 of the PCI Control Register) for its subtractive decode. Of the three choices for the sampling point: slow (5 PCI cycles), typical (4 PCI cycles) and fast (3 PCI cycles), one should be chosen that is one clock after the slowest I/O device on the PCI bus. If the PCI agents are all memory mapped above 16M Byte and all I/O mapped above 64K, then the fast sampling point for the subtractive decode can be chosen. This insures that no other PCI agent except the SIO will claim these addresses. Configure PCI agents in this manner to improve performance.

The SIO automatically inserts a 4 ISA clock cycle delay between PCI originated back-to-back 8 and 16 bit I/O cycles to the ISA bus. In addition, the ISA Controller Recovery Timer Register (configuration register, address offset=4Ch) enables a number of additional ISA clock cycles of delay to be inserted between these types of back-to-back I/O cycles. The ISA Controller Recovery Timer Register defaults (after power-on reset) to 2 additional ISA clock cycles of delay, making the total delay equal to 6 ISA clock cycles, for both the 8 and 16 bit I/O recovery times. Since none of the native I/O devices on the reference design require such long recovery times, the additional cycles specified by the ISA Controller Timer Register can be disabled. If an ISA card requiring a long recovery time is supported, the driver should insure that the recovery time is met.

Disable scatter/gather mode and GAT mode.

Do not attempt to access DMA channel 4 address and byte count registers.

Always enable the ISA master and DMA buffers. In order to isolate slow ISA Bus I/O devices from the PCI bus, the DMA controller uses the DMA/ISA master Line Buffer. This buffer can operate in single transaction or in 8-byte mode. Bits 0-LE/7-BE and 1-LE/6-BE of the PCI Control register configure the line buffer for DMA and ISA masters separately. It is required that the 8-byte mode be enabled for both (Bits = 1,1).

The registers in Table 3 must be set in order for the reference design I/O hardware to operate properly. Vendors use LE bit nomenclature, and nomenclature within CPU registers is BE.

Table 3. Summary of SIO Register Setup (Configuration Address = 8080 08xx)
Register	Addr	Bit	Set To	Reset Value	DESCRIPTION
PCI Control Register	40h	2-LE 5-BE	1	0	Enable PCI Memory Posted Write Buffer.
PCI Control Register	40h	1-LE 6-BE	1	0	Enable ISA Master Line buffer.
PCI Control Register	40h	0-LE 7-BE	1	0	Enable DMA Line Buffer.
PCI Arbiter Control (Config/ PCI)	41h	0-LE 7-BE	0	0	Disable Guaranteed Access Time (GAT) Mode. Note: GAT does not work in SIO.
ISA Clock Divisor (Config/ PCI)	4Dh	5-LE 2-BE	0	0	Disable Coprocessor Error Support.
ISA Clock Divisor (Config/ PCI)	4Dh	4-LE 3-BE	1	0	Enable IRQ12/M Mouse Support.
ISA Clock Divisor (Config/ PCI)	4Dh	3-LE 4-BE	*	0	* This bit should be set to 1 before chang ing or loading the PCI ISA Clock Divisor value. Setting this bit to 1 asserts the RSTDVR signal, which resets the System I/O EPLD and any devices on the ISA bus slots. All of these devices require reconfi guration after this bit has been asserted. Software must guarantee that RSTDVR be asserted for a minimum of 1 ms after the clock divisor value is set.
ISA Clock Divisor (Config/ PCI)	4Dh	2:0-LE 5:7-BE	*	0	* Set this field to 000b (divisor = 4). If PCI clock is slower than 33 MHz, then this field would be 001b (divisor=3).
Utility Bus Chip Select A (Config/PCI)	4Eh	4-LE 4-BE	1	0	Disable generation of ECSADDR(2:0) and UBUSOE# for the IDE and Floppy decode.
Utility Bus Chip Select A (Config/PCI)	4Eh	1-LE 6-BE	1	1	Enable keyboard addresses (60h, 62h, 64h, 66h).
Utility Bus Chip Select A (Config/PCI)	4Eh	0-LE 7-BE	1	1	Enable TOD Addresses (70h, 71h).
Utility Bus Chip Select B (Config/PCI)	4Fh	7-LE 0-BE	1	0	Enable access to the motherboard regis ters in the 0800-08FF address range.
Utility Bus Chip Select B (Config/PCI)	4Fh	6-LE 1-BE	1	1	Enable Port 92h access.
Utility Bus Chip Select B (Config/PCI)	4Fh	5:4-LE 2:3-BE	11	00	Disable generation of default address for Parallel Port.
Utility Bus Chip Select B (Config/PCI)	4Fh	3:2-LE 4:5-BE	11	00	Disable generation of default address for Serial Port B.
Utility Bus Chip Select B (Config/PCI)	4Fh	1:0-LE 6:7-BE	11	00	Disable generation of default address for Serial Port A.
Interrupt Controller 1 - ICW1 (I/O /PCI)	20h	3-LE 4-BE	0	x	Set Interrupt Controller 1 to edge triggered mode.
Interrupt Controller 1 - ICW1 (I/O /PCI)	20h	1-LE 6-BE	0	x	Set Interrupt Controller 1 to cascade mode.
Interrupt Controller 2 - ICW1 (I/O /PCI)	A0h	3-LE 4-BE	0	x	Set Interrupt Controller 2 to edge triggered mode.
Interrupt Controller 2 - ICW1 (I/O /PCI)	A0h	1-LE 6-BE	0	x	Set Interrupt Controller 2 to cascade mode.
NMI Status and Control (I/O /PCI)	61h	3-LE 4-BE	0	0	IOCHK# NMI enabled.
NMI Status and Control (I/O /PCI)	61h	2-LE 5-BE	0	0	PCI SERR# NMI enabled.
NMI Enable and TOD Ad dress (I/O /PCI)	70h	7-LE 0-BE	0	1	NMI interrupt enabled.
DMA Command (I/O /PCI)	08h, D0h	7-LE 0-BE	0	0	DACK# Assert Level set to low.
DMA Command (I/O /PCI)	08h, D0h	6-LE 1-BE	0	0	DREQ Sense Level set to high.

1.3.1 ISA Bridge PCI Configuration Registers

1.4 MPIC Initialization

• PCI configuration registers Access via PCI configuration transactions
• PCI I/O space registers Access via PCI I/O transactions

1.4.1 MPIC PCI Configuration Registers

Table 5. MPIC PCI Configuration Registers
31 24	23 16	15 8	7 0	Offset
Device ID (0046h)		Vendor ID (1014h)	00h
Status (0200h)		Command (0000h)	04h
Reserved	Reserved	Reserved	Reserved	08h
Reserved	Reserved	Reserved	Reserved	0Ch
Base Address Zero (I/O Space) ()				10h
Base Address One (Memory Space) ()				14h
Reserved				18h
				...
Reserved				FCh

1.4.2 MPIC PCI I/O Registers

1.4.2.1 MPIC Global Registers (PCI I/O)

Table 6. MPIC Global Registers (PCI I/O)
PCI I/O Offset	Name	Description	R/W	Set To	Notes
0000 1000		Feature Reporting Register 0
0000 1020		Global Configuration Register 0		Bit 29, set=1
0000 1080		Vendor ID Register
0000 1090		Processor Init Register
0000 10A0		IPI 0 Vector/Priority Register		0x800F0020
0000 10B0		IPI 1 Vector/Priority Register		0x800F0021
0000 10C0		IP12 Vector/Parity Register (Unused)		0x800F0022
0000 10D0		IP13 Vector/Parity Register (Unused)		0x800F0023
0000 10F0		Timer Frequency Reporting Register		-
0000 1100		Global Timer 0 Current Count		-
0000 1110		Global Timer 0 Base Count		-
0000 1120		Global Timer 0 Vector/Priority Register		0x80000030
0000 1130		Global Timer 0 Destination Register		-
0000 1140		Global Timer 1 Current Count		-
0000 1150		Global Timer 1 Base Count		-
0000 1160		Global Timer 1 Vector/Priority Register		0x80000031
0000 1170		Global Timer 1 Destination Register		-
0000 1180		Global Timer 2 Current Count		-
0000 1190		Global Timer 2 Base Count		-
0000 11A0		Global Timer 2 Vector/Priority Register		0x80000032
0000 11B0		Global Timer 2 Destination Register		-
0000 11C0		Global Timer 3 Current Count		-
0000 11D0		Global Timer 3 Base Count		-
0000 11E0		Global Timer 3 Vector/Priority Register		0x80000033
0000 11F0		Global Timer 3 Destination Register		-

1.4.2.2 MPIC Interrupt Source Configuration Registers (PCI I/O)

Table 7. MPIC Interrupt Source Configuration Registers (PCI I/O)
Address Offset	Name	Description	R/W	Set To	Notes
0001 0000		Interrupt Source 0 Vector/Priority		0x00CE0000
0001 0010		Interrupt Source 0 Destination		-
0001 0020		Interrupt Source 1 Vector/Priority		0x804E0011
0001 0030		Interrupt Source 1 Destination		-
0001 0040		Interrupt Source 2 Vector/Priority		0x804E0012
0001 0050		Interrupt Source 2 Destination		-
0001 0060		Interrupt Source 3 Vector/Priority		0x804E0013
0001 0070		Interrupt Source 3 Destination		-
0001 0080		Interrupt Source 4 Vector/Priority		0x804E0014
0001 0090		Interrupt Source 4 Destination		-
0001 00A0		Interrupt Source 5 Vector/Priority		0x804E0015
0001 00B0		Interrupt Source 5 Destination		-
0001 00C0		Interrupt Source 6 Vector/Priority		0x804E0016
0001 00D0		Interrupt Source 6 Destination		-
0001 00E0		Interrupt Source 7 Vector/Priority		0x804E0017
0001 00F0		Interrupt Source 7 Destination		-
0001 0100		Interrupt Source 8 Vector/Priority		0x804E0018
0001 0110		Interrupt Source 8 Destination		-
0001 0120		Interrupt Source 9 Vector/Priority		0x804E0019
0001 0130		Interrupt Source 9 Destination		-
0001 0140		Interrupt Source 10 Vector/Priority		0x804E001A
0001 0150		Interrupt Source 10 Destination		-
0001 0160		Interrupt Source 11 Vector/Priority		0x804E001B
0001 0170		Interrupt Source 11 Destination		-
0001 0180		Interrupt Source 12 Vector/Priority		0x804E001C
0001 0190		Interrupt Source 12 Destination		-
0001 01A0		Interrupt Source 13 Vector/Priority		0x804E001D
0001 01B0		Interrupt Source 13 Destination		-
0001 01C0		Interrupt Source 14 Vector/Priority		0x804E001E
0001 01D0		Interrupt Source 14 Destination		-
0001 01E0		Interrupt Source 15 Vector/Priority		0x804E001F
0001 01F0		Interrupt Source 15 Destination		-

1.4.2.3 MPIC Per Processor Registers (PCI I/O)

Table 8. MPIC Per Processor Registers (PCI I/O)
Address Offset	Name	Description	R/W	Set To	Notes
0002 0040		Processor 0 IPI 0 Dispatch		-
0002 0050		Processor 0 IPI 1 Dispatch		-
0002 0080		Processor 0 Current Task Priority		0
0002 00A0		Processor 0 Interrupt Acknowledge		-
0002 00B0		Processor 0 End of Interrupt		-
0002 1040		Processor 1 IPI 0 Dispatch		-
0002 1050		Processor 1 IPI 1 Dispatch		-
0002 1080		Processor 1 Current Task Priority		0
0002 10A0		Processor 1 Interrupt Acknowledge		-
0002 10B0		Processor 1 End of Interrupt		-

1.5 Ethernet Initialization

• PCI configuration registers Access via PCI configuration transactions
• PCI I/O space registers Access via PCI I/O transactions
• CSR and BCR registers Access using pairs of PCI I/O transactions

1.5.1 Ethernet PCI Configuration Registers

Table 9. Ethernet PCI Configuration Registers
31 24	23 16	15 8	7 0	Offset
Device ID (2000h)		Vendor ID (1022h)	00h
Status		Command	04h
Base-Class (02h)	Sub-Class (00h)	Programming IF (00h)	Revision ID (00h)	08h
Reserved	Header Type (00h)	Latency Timer (00h)	Reserved	0Ch
Base Address Zero (I/O Space) (8080 4000h)				10h
Base Address One (Memory Space)				14h
Reserved				18h
Reserved				1Ch
Reserved				20h
Reserved				24h
Reserved				28h
Expansion ROM Base Address				2Ch
Reserved				30h
Reserved				34h
Reserved				38h
MAX_LAT	MIN_GNT	Interrupt Pin	Interrupt Line	3Ch
Reserved				40h
Reserved
Reserved				FCh

1.5.2 Ethernet PCI I/O Registers

There are two modes of accessing these registers. For backwards compatibility with earlier AMD Ethernet controllers, the default mode after power up is Word I/O (WIO), in which the PCI I/O registers are mapped as 2-byte entities (see Table 10). The 79C970A can also be configured for Double Word I/O (DWIO), in which the PCI I/O registers are mapped as 4-byte entities (see Table 11). See the 79C970A data sheet for more information.

To change to DWIO, write a 4-byte value to offset 10h. Once the part is in DWIO mode, a hard reset is needed to exit. If the EEPROM programs to DWIO mode, then WIO mode can only be entered by reprogramming the EEPROM and doing a hard reset.

When in WIO mode, APROM addresses may be accessed as bytes on either even or odd addresses. Attempting 4-byte writes to the PCI I/O registers (except for offset 10h) while in WIO mode may cause unpredictable programming of the part. Four byte reads from the PCI I/O registers while in WIO mode are illegal and will produce undefined results. Two byte accesses to non-word boundaries are illegal and may produce unexpected results. Only the APROM locations may be accessed as a non-word.

When in DWIO mode all accesses must be 4-byte and 4-byte aligned. This includes the APROM locations. RDP, RAP, and BDP contain only two bytes of valid data; the other two bytes are reserved for future use (CSR88 is an exception to this rule). The reserved bytes should be written as zero and ignored when read.

The Vendor Specified Word is not implemented. This address is reserved for customer use and will not be used by future AMD ethernet controllers.

Some of this is setup information which may be stored in an external serial EEPROM.

Table 10. Ethernet I/O Map In Word I/O Mode (DWIO = 0)
Offset	Number of Bytes	Register
00h-0Fh	16	APROM
10h	2	RDP
12h	2	RAP (shared by RDP and BDP)
14h	2	Reset Register
16h	2	BDP
18h-1Ph	8	Reserved

Table 11. Ethernet I/O Map In DWord I/O Mode (DWIO = 1)
Offset	Number of Bytes	Register
00h-0Fh	16	APROM
10h	4	RDP
14h	4	RAP (shared by RDP and BDP)
18h	4	Reset Register
1Ch	4	BDP

1.5.3 Ethernet CSR and BSR Registers

The Bus Control Registers (BCR) are accessed by first writing the offset address into the RAP register, and then writing to or reading from the BDP register to effect the data transfer. The BCR registers (see Table 13) are used to configure the bus interface unit and the LEDs.

Most of the BCR and CSR registers are only programmed once, during the setup of the Ethernet controller, but there are no restrictions on the number of times that they may be accessed. If the default power up values are acceptable these registers need not be accessed at all.

Table 12. Ethernet CSR Registers
Register	Description
CSR1	Initialization Block Address[15:0]
CSR2	Initialization Block Address[31:16]
CSR3	Interrupt Masks and Deferral Control
CSR4	Test and Features Control
CSR5	Extended Control and Interrupt
CSR8	Logical Address Filter[15:0]
CSR9	Logical Address Filter[31:16]
CSR10	Logical Address Filter[47:32]
CSR11	Logical Address Filter[63:48]
CSR12	Physical Address[15:0]
CSR13	Physical Address[31:16]
CSR14	Physical Address[47:32]
CSR15	Mode
CSR24	Base Address of Receive Descriptor Ring Lower
CSR25	Base Address of Receive Descriptor Ring Upper
CSR30	Base Address of Transmit Descriptor Ring Lower
CSR31	Base Address of Transmit Descriptor Ring Upper
CSR47	Polling Interval
CSR76	Receive Descriptor Ring Length
CSR78	Transmit Descriptor Ring Length
CSR82	Bus Activity Timer
CSR100	Memory Error Timeout
CSR122	Receiver Packet Alignment Control

Table 13. Ethernet BCR Registers
Register	Description
BCR2	Miscellaneous Configuration
BCR4	Link Status LED
BCR5	LED1 Status
BCR6	LED2 Status
BCR7	LED3 Status
BCR9	Full-Duplex Control
BCR18	Bus and Burst Control
BCR20	Software Style

1.5.4 Ethernet EEPROM Interface

While the Ethernet controller supports reading and writing to an external serial EEPROM, the reference design only implements reading the serial EEPROM (the EEPROM write enable control is not implemented). The EEPROM is socketed to allow for external reprogramming.

The serial EEPROM used in the reference design is a 64 x 16 bit device which resides in an 8 pin dip socket. Table 14 shows the EEPROM contents and their suggested programming values. Different implementations may require a change to some or all of the suggested values. The automatic EEPROM read operation will access 36 bytes.

Table 14. Ethernet EEPROM Content
Byte Address	Description	Initial Value
00h	First byte of the ISO 8802-3 (IEEE/ANSI 802.3) station physical address for this node, where first byte refers to first byte to appear on the 802.3 medium	08
01h	Second byte of the ISO 8802-3 station physical address for this node	00
02h	Third byte of the node address	5A
03h	Fourth byte of the node address	FC
04h	Fifth byte of the node address	02
05h	Sixth byte of the node address	0F
06h	Reserved location: must be 00h	00
07h	Reserved location: must be 00h	00
08h	Reserved location: must be 00h	00
09h	Hardware ID: must be 11h if compatibility to AMD drivers is desired	10
0Ah	User programmable space	00
0Bh	User programmable space	00
0Ch	LSByte of 2-byte checksum, which is the sum of bytes 00h-0Bh and bytes 0Eh and 0Fh	2E
0Dh	MSByte of 2-byte checksum, which is the sum of bytes 00h-0Bh and bytes 0Eh and 0Fh	02
0Eh	Must be ASCII W (57h) if compatibility to AMD driver software is desired	57
0Fh	Must be ASCII W (57h) if compatibility to AMD driver software is desired	57
10h	BCR4[7:0] (Link Status LED)	00
11h	BCR4[15:8] (Link Status LED)	00
12h	BCR5[7:0] (LED1 Status)	00
13h	BCR5[15:8] (LED1 Status)	00
14h	BCR18[7:0] (Burst and Bus Control)	81
15h	BCR18[15:8] (Burst and Bus Control)	21
16h	BCR2[7:0] (Miscellaneous Configuration)	06
17h	BCR2[15:8] (Miscellaneous Configuration)	00
18h	BCR6[7:0] (LED2 Status)	00
19h	BCR6[15:8] (LED2 Status)	00
1Ah	BCR7[7:0] (LED3 Status)	00
1Bh	BCR7[15:8] (LED3 Status)	00
1Ch	BCR9[7:0] (Full-Duplex Control)	00
1Dh	BCR9[15:8] (Full-Duplex Control)	00
1Eh	Reserved location must be 00h	00
1Fh	Checksum adjust byte for the first 36 bytes of the EEPROM contents, checksum of the first 36 bytes of the EEPROM should total to FFh	F4
20h	BCR22[7:0] (PCI Latency)	06
21h	BCR22[15:8] (PCI Latency)	FF
22h	Reserved location must be 00h	00
23h	Reserved location must be 00h	00

1.6 SCSI Initialization

• PCI configuration registers Access via PCI configuration transactions
• PCI I/O space registers Access via PCI I/O transactions

1.6.1 SCSI PCI Configuration Registers

This reference design uses PCI_AD[12] (device number 2) to activate the SCSI controller IDSEL during PCI configuration transactions.

Table 15. SCSI PCI Configuration Registers
31 24	23 16	15 8	7 0	Offset
Device ID (0001h)		Vendor ID (1000h)	00h
Status		Command	04h
Base-Class (00h)	Sub-Class (00h)	Programming IF (00h)	Revision ID (01h)	08h
Not Supported	Header Type (00h)	Latency Timer	Not Supported	0Ch
Base Address Zero (I/O Space)				10h
Base Address One (Memory Space)				14h
Reserved				18h
Reserved				1Ch
Reserved				20h
Reserved				24h
Reserved				28h
Expansion ROM Base Address				2Ch
Reserved				30h
Reserved				34h
Reserved				38h
MAX_LAT	MIN_GNT	Interrupt Pin	Interrupt Line	3Ch
Reserved				40h
Reserved
Reserved				FCh

1.6.2 SCSI PCI I/O Registers

Table 16. SCSI PCI I/O Registers
Offset	Name	R/W	Set To	Note
00	SCSI Control 0		0xC0
01	SCSI Control 1		0x00
02	SCSI Control 2		0x00
03	SCSI Control 3		0x33
04	SCSI Chip ID		0x07
05	SCSI Transfer		-
06	SCSI Destination OD		-
07	General Purpose Bits		0x0
08	SCSI First Byte Received		-
09	SCSI Output Control Latch		-
0A	SCSI Selector ID		-
0B	SCSI Bus Control Lines		-
0C	DMA Status		-
0D	SCSI Status 0		-
0E	SCSI Status 1		-
0F	SCSI Status 2		-
10-13	Data Structure Address		-
14	Interrupt Status		-	1
18	Chip Test 0		0x0
19	Chip Test 1		-
1A	Chip Test 2		-
1B	Chip Test 3		-
1C-1F	Temporary Stack		-
20	DMA FIFO		-
21	Chip Test 4		-
22	Chip Test 5		-
23	Chip Test 6		-
24-26	DMA Byte Counter		-
27	DMA Command		-
28-2B	DMA Next Address for Data		-
2C-2F	DMA SCRIPTS Pointer		-
30-33	DMA SCRIPTS Pointer Save		-
34-37	General Purpose Scratch Pad A		-
38	DMA Mode		0xC0
39	DMA Interrupt Enable		0x7D
3A	DMA Watchdog Timer		-
3B	DMA Control		0x09
3C-3F	Sum Output of Internal Adder		-
40	SCSI Interrupt Enable 0		0x8E
41	SCSI Interrupt Enable 1		0x04
42	SCSI Interrupt Status 0		-
43	SCSI Interrupt Status 1		-
44	SCSI Longitudinal Parity		-
45	Reserved		-
46	Memory Access Control		-
47	General Purpose Control		-
48	SCSI Timer 0		0xB0
49	SCSI Timer 1		-
4A	Response ID		-
4B	Reserved		-
4C	SCSI Test 0		-
4D	SCSI Test 1		-
4E	SCSI Test 2		-
4F	SCSI Test 3		0x80
50	SCSI Input Data Latch		-
51-53	Reserved		-
54	SCSI Output Data Latch		-
55-57	Reserved		-
58	SCSI Bus Data Lines		-
59-5B	Reserved		-
5C-5F	General Purpose Scratch Pad B		-
60-7F	Reserved		-
80-FF	(Repeat 00-7F)		-
Notes: The only accessible register when SCRIPTS is executing is the interrupt status register.

1.7 SuperI/O Initialization

• Pin strap configuration
• Configuration register configuration
• Controller register accesses

1.7.1 SuperI/O Pin Strap Configuration

• VLD[1:0] affect the state of the FDC Tape Drive register (3F3h).
• CFG[4:0] affect the configuration of the Super I/O.
• BADDR[1:0] sets the base addresses of the Index Register and the Data Register.

1.7.2 SuperI/O Configuration Register Configuration

Table 17. SuperI/O BADDR Encoding
BADDR1	BADDR0	Index Register Address	Data Register Address
0	0	398h	399h
0	1	26Eh	26Fh
1	0	15Ch	15Dh
1	1	2Eh	2Fh

The configuration registers are indirectly (two accesses required) accessed from the ISA bus. To access a given configuration register, first write the index (see Table 18) of the register into the Index register. To read (or write) the register pointed to by the Index register, read (or write) the Data register.

Table 18. SuperI/O Configuration Registers (ISA Bus Indirect Access)
Index	Name	Description
00	FER	Function Enable Register
01	FAR	Function Address Register
02	PTR	Power & Test Register
03	FCR	Function Control Register
04	PCR	Printer Control Register
06	PMC	Power Management Control Register
07	TUP	Tape, UARTs, and Parallel Port Configuration Register
08	SID	SuperI/O Identification Register

1.7.3 SuperI/O Controller Register Access

1.7.3.1 SuperI/O FDC Registers

Table 19. SuperI/O FDC Registers (ISA I/O)
Index	Name	R/W	Description
0	SRA	R	Status Register A
1	SRB	R	Status Register B
2	DOR	R/W	Digital Output Register
3	TDR	R/W	Tape Drive Register
4	MSR	R	Main Status Register
4	DSR	W	Data Rate Select Register
5	FIFO	R/W	Data Register (FIFO)
6		X	None (Bus Tristate)
7	DIR	R	Digital Input Register
7	CCR	W	Configuration Control Register

1.7.3.2 SuperI/O UART Registers

Table 20. SuperI/O UART Registers (One Set Per UART) (ISA I/O)
DLAB	Index	Name	R/W	Description
0	0		R	Receiver Buffer
0	0		W	Transmitter Holding
0	1	IER	R/W	Interrupt Enable Register
0	2	IIR	R	Interrupt Identification Register
0	2	FCR	W	FIFO Control Register
x	3	LCR	R/W	Line Control Register
x	4	MCR	R/W	Modem Control Register
x	5	LSR	R/W	Line Status Register
x	6	MSR	R	Modem Status Register
x	7	SCR	R/W	Scratchpad Register
1	0			Divisor Latch (Least Significant Byte)
1	1			Divisor Latch (Most Significant Byte)

1.7.3.3 SuperI/O Parallel Port Registers

Table 21. SuperI/O Parallel Port Registers(ISA I/O)
Index	Name	R/W	Description
0		R/W	Data
1		R	Status
2		R/W	Control
3			None (Bus Tristate)

1.7.3.4 SuperI/O IDE Registers

Table 22. SuperI/O IDE Registers(ISA I/O)
Address	Read Function	Write Function
1F0	Data	Data
1F1	Error	Features
1F2	Sector Count	Sector Count
1F3	Sector Number	Sector Number
1F4	Cylinder Low	Cylinder Low
1F5	Cylinder High	Cylinder High
1F6	Drive/Head	Drive/Head
1F7	Status	Command
3F6	Alternate Status	Device Control
3F7	Drive Address (except D7)	Not Used (3S)

1.8 Business Audio Initialization

Refer to the CS4232 manual for chip setup information. The motherboard imposes a set-up requirement that the XCTL0 bit of Pin Control register I10 be set to 1 following power-on in order to enable the internal speaker. XCTL0 defaults to 0b in order to mute the speaker during power-on. The mono microphone input should be muted prior to demuting the speaker. The mono microphone input should be used only when the mono output of the chip is internally muted; otherwise, undesirable feedbacks may occur. XCTL0 mutes both the timer 2 output and the mono output of the chip when it is zero. It should, therefore, be set to 1 for normal operation.

1.8.1 CS4232 Initialization

The initialization key should be written to ISA IO address 0x279. This is system address 0x80000279. The key consist of the following 32 bytes:

0x96, 0x35, 0x9A, 0xCD, 0xE6, 0xF3, 0x79, 0xBC,
0x5E, 0xAF, 0x57, 0x2B, 0x15, 0x8A, 0xC5, 0xE2,
0xF1, 0xF8, 0x7C, 0x3E, 0x9F, 0x4F, 0x27, 0x13,
0x09, 0x84, 0x42, 0xA1, 0xD0, 0x68, 0x34, 0x1A .

Before writing the key, 0 should be written to port 0x279 twice.

After writing each byte to port 0x279, wait for 250 micro-seconds before writing the next. After the key is sent, the chip enters its Config State. After the chip is configured, it must be placed back into the Wait-for-Key state to be used. This is done by sending the WAIT_FOR_KEY command (0x79) to port 0x279.

1.8.1.1 Config State

In the config state, each logical device in the chip may be configured. Base address, DMA channels, and interrupt levels for each logical device may be configured independently. Also, each logical device may be activated or deactivated.

Table 23 and Table 24 show how the numbers used to assign channels map to the system channels. These are the only settings which may be used for assigning DMA and interrupt channels. Notice that the only item that does not have a one-to-one correspondence is interrupt level 14.

Table 23. Settings for DMA Channels
To Use DMA Channel	Program CS4232 Setting For:
0	0
1	1
3	3

Table 24. Settings for Interrupt Channels
To Use Interrupt Level	Program CS4232 Setting For (Interrupt Descriptor):
5	5
7	7
9	9
11	11
12	12
14	15

To configure the part, a series of commands are sent to port 0x279. Each command is a byte followed by one or more data bytes. The number of data bytes depends upon the command, but it is fixed for a particular command. To configure a logical device, first select it with the DEVICE command. Then use the remaining commands to configure the device. Table 25 lists the valid commands.

Table 25. Device Configuration Commands
Command	Description	Code
DEVICE	Select logical device to configure	0x15
ADDRESS0	Select base address number 0	0x47
ADDRESS1	Select base address number 1	0x48
ADDRESS2	Select base address number 2	0x42
INT0	Select interrupt 0 level	0x22
INT1	Select interrupt 1 level	0x27
DMA0	Select dma 0 channel	0x2A
DMA1	Select dma 1 channel	0x25
ACTIVATE	Activate logical device	0x33
WAIT_FOR_KEY	Wait for key	0x79

1.8.1.2 Device

The device command is followed by one byte. This byte selects a logical device for configuration. After selecting a logical device the other commands may be used to configure it. The logical devices for the CS4232 and their identifiers are found in Table 26.

Table 26. CS4232 Logical Devices
Device	Logical Device Number
Windows Sound System/ OPL3/Sound Blaster Pro	0
Game Port	1
CS4232 Control	2
MPU-401	3
CD-ROM	4

The resources required by each logical device vary. Table 27 lists the maximum of each type of resource is associated with each logical device.

Table 27. Logical Device Resources
Logical Device	Base Addresses	Interrupt Levels	DMA Channels
0	3	1	2
1	1	0	0
2	1	1	0
3	1	1	0
4	1	1	1

1.8.1.3 ADDRESS0, ADDRESS1, ADDRESS2

These commands are followed by two bytes. The first byte is the high byte of the address, the second is the low byte of the address. Only logical device 0 uses other than ADDRESS0. The descriptions for logical device 0 are found in Table 28.

Table 28. Base Address Commands
Base Address Command	Logical Device 0 Description
ADDRESS0	Windows Sound System
ADDRESS1	OPL3
ADDRESS2	Sound Blaster Pro

The Windows Sound System is the four registers that were available in the CS4231.

1.8.1.4 INT0, INT1

These commands are followed by one byte that gives the interrupt descriptor for the item being configured. The command used determines the descriptor level of the interrupt being configured. INT0 programs determine descriptor level 0. INT1 programs determine descriptor level 1. There are no documented uses of INT1. Each logical device has a maximum of 1 interrupt level.

1.8.1.5 DMA0, DMA1

These commands are followed by one byte. This byte gives the DMA channel. Only logical device 0 uses more than one channel. DMA commands are shown in Table 29.

Table 29. DMA Channels
DMA command	DMA description for logical device 0
DMA0	Playback
DMA1	Capture

1.8.1.6 ACTIVATE

The activate command is followed by one byte which tells whether to turn on or off the current logical device. On/off commands are shown in Table 30.

Table 30. Activate Commands
Action	Value
Turn on	1
Turn off	0

1.8.1.7 WAIT_FOR_KEY

This command signals the end of CS4232 configuration. The chips will look for its key at address 0x279, allowing it to be reconfigured.

1.9 Reference Design Combined Register Listing

1.9.1 ISA Registers

Table 31 contains a summary listing of the registers that are physically located in the reference design motherboard. In general, these registers are accessed using single CPU transfers. There is an additional set of registers (see Table 31) located in the 660 bridge, which are accessed using pairs of CPU transfers.

Table 31. Combined Direct Access ISA Bus I/O Register Listing
ISA Port	Contiguous Mode Addr1	Non-Contig Mode Addr1	Description	R/W	Set To2	Loc3	Note
0000	8000 0000	8000 0000	DMA1 CH0 Base and Current Addr	R/W	-	SIO
0001	8000 0001	8000 0001	DMA1 CH0 Base and Current Cnt	R/W	-	SIO
0002	8000 0002	8000 0002	DMA1 CH1 Base and Current Addr	R/W	-	SIO
0003	8000 0003	8000 0003	DMA1 CH0 Base and Current Cnt	R/W	-	SIO
0004	8000 0004	8000 0004	DMA1 CH2 Base and Current Addr	R/W	-	SIO
0005	8000 0005	8000 0005	DMA1 CH2 Base and Current Cnt	R/W	-	SIO
0006	8000 0006	8000 0006	DMA1 CH3 Base and Current Addr	R/W	-	SIO
0007	8000 0007	8000 0007	DMA1 CH3 Base and Current Cnt	R/W	-	SIO
0008	8000 0008	8000 0008	DMA1 Status(R) Command(W)	R/W	-	SIO
0009	8000 0009	8000 0009	DMA1 Soft Request	W	-	SIO
000A	8000 000A	8000 000A	DMA1 Write Single Mask Bit	W	-	SIO
000B	8000 000B	8000 000B	DMA1 Write Mode	W	-	SIO
000C	8000 000C	8000 000C	DMA1 Clear Byte Pointer	W	-	SIO
000D	8000 000D	8000 000D	DMA1 Master Clear	W	-	SIO
000E	8000 000E	8000 000E	DMA1 Clear Mask	W	-	SIO
000F	8000 000F	8000 000F	DMA1 R/W All Mask Register Bits	R/W	-	SIO
0020	8000 0020	8000 1000	INT1 Control	R/W	-	SIO
0021	8000 0021	8000 1001	INT1 Mask	R/W	-	SIO
0040	8000 0040	8000 2000	Timer Counter 1 - Counter 0 Cnt	R/W	-	SIO
0041	8000 0041	8000 2001	Timer Counter 1 - Counter 1 Cnt	R/W	-	SIO
0042	8000 0042	8000 2002	Timer Counter 1 - Counter 2 Cnt	R/W	-	SIO
0043	8000 0043	8000 2003	Timer Counter 1 Command Mode	W	-	SIO
0060	8000 0060	8000 3000	Reset X-Bus (Mouse) IRQ12 and Keyboard	R	-	SIO
0061	8000 0061	8000 3001	NMI Status and Control	R/W	-	SIO
0062	8000 0062	8000 3002	Reserved for Keyboard/Mouse	R/W	-	KBD	4
0064	8000 0064	8000 3004	Keyboard/Mouse	R	-	KBD	4
0066	8000 0066	8000 3006	Reserved for Keyboard/Mouse	R/W	-	KBD	4
0070	8000 0070	8000 3010	RTC Addr and NMI Enable	W	-	SIO
0071	8000 0071	8000 3011	RTC Read/Write	R/W	-	RTC	4
0074	8000 0074	8000 3014	NV RAM Addr Strobe 0	W	-	NVR	4
0075	8000 0075	8000 3015	NV RAM Addr Strobe 1	W	-	NVR	4
0077	8000 0077	8000 3017	NV RAM Data Port	R/W	-	NVR	4
0078	8000 0078	8000 3018	BIOS Timer	R/W	-	SIO
0079	8000 0079	8000 3019	BIOS Timer	R/W	-	SIO
007A	8000 007A	8000 301A	BIOS Timer	R/W	-	SIO
007B	8000 007B	8000 301B	BIOS Timer	R/W	-	SIO
0080	8000 0080	8000 4000	DMA Page Register Reserved	R/W	-	SIO
0081	8000 0081	8000 4001	DMA Channel 2 Page Register	R/W	-	SIO
0082	8000 0082	8000 4002	DMA Channel 3 Page Register	R/W	-	SIO
0083	8000 0083	8000 4003	DMA Channel 1 Page Register	R/W	-	SIO
0084	8000 0084	8000 4004	DMA Page Register Reserved	R/W	-	SIO
0085	8000 0085	8000 4005	DMA Page Register Reserved	R/W	-	SIO
0086	8000 0086	8000 4006	DMA Page Register Reserved	R/W	-	SIO
0087	8000 0087	8000 4007	DMA Channel 0 Page Register	R/W	-	SIO
0088	8000 0088	8000 4008	DMA Page Register Reserved	R/W	-	SIO
0089	8000 0089	8000 4009	DMA Channel 6 Page Register	R/W	-	SIO
008A	8000 008A	8000 400A	DMA Channel 7 Page Register	R/W	-	SIO
008B	8000 008B	8000 400B	DMA Channel 5 Page Register	R/W	-	SIO
008C	8000 008C	8000 400C	DMA Page Register Reserved	R/W	-	SIO
008D	8000 008D	8000 400D	DMA Page Register Reserved	R/W	-	SIO
008E	8000 008E	8000 400E	DMA Page Register Reserved	R/W	-	SIO
008F	8000 008F	8000 400F	DMA Low Page Register Refresh	R/W	-	SIO
0090	8000 0090	8000 4010	DMA Page Register Reserved	R/W	-	SIO
0092	8000 0092	8000 4012	Special Port 92 Register	R/W	-	660
0094	8000 0094	8000 4014	DMA Page Register Reserved	R/W	-	SIO	5
0095	8000 0095	8000 4015	DMA Page Register Reserved	R/W	-	SIO
0096	8000 0096	8000 4016	DMA Page Register Reserved	R/W	-	SIO
0098	8000 0098	8000 4018	DMA Page Register Reserved	R/W	-	SIO
009C	8000 009C	8000 401C	DMA Page Register Reserved	R/W	-	SIO
009D	8000 009D	8000 401D	DMA Page Register Reserved	R/W	-	SIO
009E	8000 009E	8000 401E	DMA Page Register Reserved	R/W	-	SIO
009F	8000 009F	8000 401F	DMA Low Page Register Refresh	R/W	-	SIO
00A0	8000 00A0	8000 5000	INT2 Control Register	R/W	-	SIO
00A1	8000 00A1	8000 5001	INT2 Mask Register	R/W	-	SIO
00C0	8000 00C0	8000 6000	DMA2 CH0 Base and Current Addr	R/W	-	SIO
00C2	8000 00C2	8000 6002	DMA2 CH0 Base and Current Cnt	R/W	-	SIO
00C4	8000 00C4	8000 6004	DMA2 CH1 Base and Current Addr	R/W	-	SIO
00C6	8000 00C6	8000 6006	DMA2 CH1 Base and Current Cnt	R/W	-	SIO
00C8	8000 00C8	8000 6008	DMA2 CH2 Base and Current Addr	R/W	-	SIO
00CA	8000 00CA	8000 600A	DMA2 CH2 Base and Current Cnt	R/W	-	SIO
00CC	8000 00CC	8000 600C	DMA2 CH3 Base and Current Addr	R/W	-	SIO
00CE	8000 00CE	8000 600E	DMA2 CH3 Base and Current Cnt	R/W	-	SIO
00D0	8000 000D	8000 6010	DMA2 Status(R) Command(W)	R/W	-	SIO
00D2	8000 00D2	8000 6012	DMA2 Soft Request	W	-	SIO
00D4	8000 00D4	8000 6014	DMA2 Write Single Mask Bit	W	-	SIO
00D6	8000 00D6	8000 6016	DMA2 Write Mode	W	-	SIO
00D8	8000 00D8	8000 6018	DMA2 Clear Byte Pointer	W	-	SIO
00DA	8000 00DA	8000 601A	DMA2 Master Clear	W	-	SIO
00DC	8000 00DC	8000 601C	DMA2 Clear Mask	W	-	SIO
00DE	8000 00DE	8000 601E	DMA2 R/W All Mask Register Bits	R/W	-	SIO
00F0	8000 00F0	8000 7010	Coprocessor Error Reg - Reserved	R/W	-	SIO
01F0- 01F7	8000 01F0-7	8000 F010-7	IDE Register 0	R/W	xx	332
0200	8000 0200		Game Port			AUD
0220- 0223	8000 0220-3		Sound Blaster L/R FM Registers	R/W		AUD
0224	8000 0224		Sound Blaster Mixer Address Register	R/W		AUD
0225	8000 0225		Sound Blaster Mixer Data Register	R/W		AUD
0226	8000 0226		Sound Blaster Reset Register	W/O		AUD
022A	8000 022A		Sound Blaster Read Data Port	W/O		AUD
022C	8000 022C		Sound Blaster Command/Status	W/O		AUD
0278	8000 0278	8001 3018	LPT 3	R/W	xx	332
0279	8000 0279	8001 3019	LPT 3	R/W	xx	332
027A	8000 027A	8001 301A	LPT 3	R/W	xx	332
027B	8000 027B	8001 301B	LPT 3	R/W	xx	332
027C	8000 027C	8001 301C	LPT 3	R/W	xx	332
027D	8000 027D	8001 301D	LPT 3	R/W	xx	332
027E	8000 027E	8001 301E	LPT 3	R/W	xx	332
027F	8000 027F	8001 301F	LPT 3	R/W	xx	332
02E0	8000 02E0	8001 7000	COM 4 Tertiary	R/W	xx	332	6
02E1	8000 02E1	8001 7001	COM 4 Tertiary	R/W	xx	332	6
02E2	8000 02E2	8001 7002	COM 4 Tertiary	R/W	xx	332	6
02E3	8000 02E3	8001 7003	COM 4 Tertiary	R/W	xx	332	6
02E4	8000 02E4	8001 7004	COM 4 Tertiary	R/W	xx	332	6
02E5	8000 02E5	8001 7005	COM 4 Tertiary	R/W	xx	332	6
02E6	8000 02E6	8001 7006	COM 4 Tertiary	R/W	xx	332	6
02E7	8000 02E7	8001 7007	COM 4 Tertiary	R/W	xx	332	6
02E8	8000 02E8	8001 7008	COM 3 or COM 4	R/W	xx	332	6
02E9	8000 02E9	8001 7009	COM 3 or COM 4	R/W	xx	332	6
02EA	8000 02EA	8001 700A	COM 3 or COM 4	R/W	xx	332	6
02EB	8000 02EB	8001 700B	COM 3 or COM 4	R/W	xx	332	6
02EC	8000 02EC	8001 700C	COM 3 or COM 4	R/W	xx	332	6
02ED	8000 02ED	8001 700D	COM 3 or COM 4	R/W	xx	332	6
02EE	8000 02EE	8001 700E	COM 3 or COM 4	R/W	xx	332	6
02EF	8000 02EF	8001 700F	COM 3 or COM 4	R/W	xx	332	6
02F8	8000 02F8	8001 7018	COM 2	R/W	xx	332
02F9	8000 02F9	8001 7019	COM 2	R/W	xx	332
02FA	8000 02FA	8001 701A	COM 2	R/W	xx	332
02FB	8000 02FB	8001 701B	COM 2	R/W	xx	332
02FC	8000 02FC	8001 701C	COM 2	R/W	xx	332
02FD	8000 02FD	8001 701D	COM 2	R/W	xx	332
02FE	8000 02FE	8001 701E	COM 2	R/W	xx	332
02FF	8000 02FF	8001 701F	COM 2	R/W	xx	332
0330	8000 0330		MIDI Transmit/Receive Register			AUD
0331	8000 0331		MIDI Status/Command Register			AUD
0338	8000 0338	8001 9018	COM 3 Primary	R/W	xx	332	7
0339	8000 0339	8001 9019	COM 3 Primary	R/W	xx	332	7
033A	8000 033A	8001 901A	COM 3 Primary	R/W	xx	332	7
033B	8000 033B	8001 901B	COM 3 Primary	R/W	xx	332	7
033C	8000 033C	8001 901C	COM 3 Primary	R/W	xx	332	7
033D	8000 033D	8001 901D	COM 3 Primary	R/W	xx	332	7
033E	8000 033E	8001 901E	COM 3 Primary	R/W	xx	332	7
033F	8000 033F	8001 901F	COM 3 Primary	R/W	xx	332	7
0370- 0377			Secondary Floppy (Reserved)			332
0378	8000 0378	8001 B018	LPT 2	R/W	xx	332	6
0379	8000 0379	8001 B019	LPT 2	R/W	xx	332	6
037A	8000 037A	8001 B01A	LPT 2	R/W	xx	332	6
037B	8000 037B	8001 B01B	LPT 2	R/W	xx	332	6
037C	8000 037C	8001 B01C	LPT 2	R/W	xx	332	6
037D	8000 037D	8001 B01D	LPT 2	R/W	xx	332	6
037E	8000 037E	8001 B01E	LPT 2	R/W	xx	332	6
037F	8000 037F	8001 B01F	LPT 2	R/W	xx	332	6
0388
0389
038A
038B
0398	8000 0398	8001 C018	Super I/O Index Address	R/W	xx	332
0399	8000 0399	8001 C019	Super I/O Data Address	R/W	xx	332
03BC	8000 03BC	8001 D01C	LPT 1	R/W	xx	332
03BD	8000 03BD	8001 D01D	LPT 1	R/W	xx	332
03BE	8000 03BE	8001 D01E	LPT 1	R/W	xx	332
03E8	8000 03E8	8001 F008	COM 3	R/W	xx	332	6
03E9	8000 03E9	8001 F009	COM 3	R/W	xx	332	6
03EA	8000 03EA	8001 F00A	COM 3	R/W	xx	332	6
03EB	8000 03EB	8001 F00B	COM 3	R/W	xx	332	6
03EC	8000 03EC	8001 F0OC	COM 3	R/W	xx	332	6
03ED	8000 03ED	8001 F00D	COM 3	R/W	xx	332	6
03EE	8000 03EE	8001 F00E	COM 3	R/W	xx	332	6
03EF	8000 03EF	8001 F00F	COM 3	R/W	xx	332	6
03F0	8000 03F0	8001 F010	Primary Floppy Digital Output	W	xx	332	8
03F1	8000 03F1	8001 F011	Primary Floppy Digital Output	W	xx	332	8
03F2	8000 03F2	8001 F012	Primary Floppy Digital Output	W	xx	332	8, 9
03F3	8000 03F3	8001 F013	Primary Floppy Digital Output (Also, Media Sense)	W	xx	332	8
03F4	8000 03F4	8001 F014	Primary Floppy Digital Output	W	xx	332	8
03F5	8000 03F5	8001 F015	Primary Floppy Digital Output	W	xx	332	8
03F6	8000 03F6	8001 F016	IDE Register 1 (Reserved)	W	xx	332	8
03F7	8000 03F7	8001 F017	IDE Register 1 (Reserved)	W	xx	332	8
03F8	8000 03F8	8001 F018	COM 1	R/W	xx	332
03FA	8000 03FA	8001 F01A	COM 1	R/W	xx	332
03FB	8000 03FB	8001 F01B	COM 1	R/W	xx	332
03FC	8000 03FC	8001 F01C	COM 1	R/W	xx	332
03FD	8000 03FD	8001 F01D	COM 1	R/W	xx	332
03FE	8000 03FE	8001 F01E	COM 1	R/W	xx	332
03FF	8000 03FF	8001 F01F	COM 1	R/W	xx	332
040B	8000 040B	8002 0006	DMA1 Extended Mode	W	-	SIO
0410	8000 0410	8002 0010	CH0 Scatter/Gather Command	W	-	SIO
0411	8000 0411	8002 0011	CH1 Scatter/Gather Command	W	-	SIO
0412	8000 0412	8002 0012	CH2 Scatter/Gather Command	W	-	SIO
0413	8000 0413	8002 0013	CH3 Scatter/Gather Command	W	-	SIO
0415	8000 0415	8002 0015	CH5 Scatter/Gather Command	W	-	SIO
0416	8000 0416	8002 0016	CH6 Scatter/Gather Command	W	-	SIO
0417	8000 0417	8002 0017	CH7 Scatter/Gather Command	W	-	SIO
0418	8000 0418	8002 0018	CH0 Scatter/Gather Status	R	-	SIO
0419	8000 0419	8002 0019	CH1 Scatter/Gather Status	R	-	SIO
041A	8000 041A	8002 001A	CH2 Scatter/Gather Status	R	-	SIO
041B	8000 041B	8002 001B	CH3 Scatter/Gather Status	R	-	SIO
041D	8000 041D	8002 001D	CH5 Scatter/Gather Status	R	-	SIO
041E	8000 041E	8002 001E	CH6 Scatter/Gather Status	R	-	SIO
041F	8000 041F	8002 001F	CH7 Scatter/Gather Status	R	-	SIO
0420	8000 0420	8002 1000	CH0 Scatter/Gather Pointer	R/W	-	SIO
0421	8000 0421	8002 1001	CH0 Scatter/Gather Pointer	R/W	-	SIO
0422	8000 0422	8002 1002	CH0 Scatter/Gather Pointer	R/W	-	SIO
0423	8000 0423	8002 1003	CH0 Scatter/Gather Pointer	R/W	-	SIO
0424	8000 0424	8002 1004	CH1 Scatter/Gather Pointer	R/W	-	SIO
0425	8000 0425	8002 1005	CH1 Scatter/Gather Pointer	R/W	-	SIO
0426	8000 0426	8002 1006	CH1 Scatter/Gather Pointer	R/W	-	SIO
0427	8000 0427	8002 1007	CH1 Scatter/Gather Pointer	R/W	-	SIO
0428	8000 0428	8002 1008	CH2 Scatter/Gather Pointer	R/W	-	SIO
0429	8000 0429	8002 1009	CH2 Scatter/Gather Pointer	R/W	-	SIO
042A	8000 042A	8002 100A	CH2 Scatter/Gather Pointer	R/W	-	SIO
042B	8000 042B	8002 100B	CH2 Scatter/Gather Pointer	R/W	-	SIO
042C	8000 042C	8002 100C	CH3 Scatter/Gather Pointer	R/W	-	SIO
042D	8000 042D	8002 100D	CH3 Scatter/Gather Pointer	R/W	-	SIO
042E	8000 042E	8002 100E	CH3 Scatter/Gather Pointer	R/W	-	SIO
042F	8000 042F	8002 100F	CH3 Scatter/Gather Pointer	R/W	-	SIO
0434	8000 0434	8002 1014	CH5 Scatter/Gather Pointer	R/W	-	SIO
0435	8000 0435	8002 1015	CH5 Scatter/Gather Pointer	R/W	-	SIO
0436	8000 0436	8002 1016	CH5 Scatter/Gather Pointer	R/W	-	SIO
0437	8000 0437	8002 1017	CH5 Scatter/Gather Pointer	R/W	-	SIO
0438	8000 0438	8002 1018	CH6 Scatter/Gather Pointer	R/W	-	SIO
0439	8000 0439	8002 1019	CH6 Scatter/Gather Pointer	R/W	-	SIO
043A	8000 043A	8002 101A	CH6 Scatter/Gather Pointer	R/W	-	SIO
043B	8000 043B	8002 101B	CH6 Scatter/Gather Pointer	R/W	-	SIO
043C	8000 043C	8002 101C	CH7 Scatter/Gather Pointer	R/W	-	SIO
043D	8000 043D	8002 101D	CH7 Scatter/Gather Pointer	R/W	-	SIO
043E	8000 043E	8002 101E	CH7 Scatter/Gather Pointer	R/W	-	SIO
043F	8000 043F	8002 101F	CH7 Scatter/Gather Pointer	R/W	-	SIO
0481	8000 0481	8002 4001	DMA CH2 High Page	R/W	-	SIO
0482	8000 0482	8002 4002	DMA CH3 High Page	R/W	-	SIO
0483	8000 0483	8002 4003	DMA CH1 High Page	R/W	-	SIO
0487	8000 0487	8002 4007	DMA CH0 High Page	R/W	-	SIO
0489	8000 0489	8002 4009	DMA CH6 High Page	R/W	-	SIO
048A	8000 048A	8002 400A	DMA CH7 High Page	R/W	-	SIO
048B	8000 048B	8002 400B	DMA CH5 High Page	R/W	-	SIO
04D0	8000 04D0	8002 6010	Interrupt Control 1	R/W	-	SIO
04D1	8000 04D1	8002 6011	Interrupt Control 2	R/W	-	SIO
04D6	8000 04D6	8002 6016	DMA2 Extended Mode	W	-	SIO
0534	8000 0534	8002 9014	Audio chip index address register	R/W		AUD
0535	8000 0535	8002 9015	Audio chip indexed data register	R/W		AUD
0536	8000 0536	8002 9016	Audio chip status register	R		AUD
0537	8000 0537	8002 9017	Audio chip PIO data register	W/O		AUD
0538	8000 0538	8002 9017	Audio chip control register 0			AUD
0808	8000 0808	8004 0008	HDD Light	R/W	-	EPLD
080C	8000 080C	8004 000C	Equipment Present	R	-	logic	4
080D	8000 080D	8004 000D	L2 Cache Status Reg	R	-	logic	4
0814	8000 0814	8004 0014	L2 Flush	W	-	660
081C	8000 081C	8004 001C	System Control 81C	R/W	10	660
0821	8000 0821	8004 1001	Memory Controller Misc	R/W	-	660
082A	8000 082A	8004 100A	Power Mgmt Control Reg1	R/W	-	EPLD	11
082B	8000 082B	8004 100B	Power Mgmt Control Reg2	R/W	-	EPLD	11
0838			Interrupt Request 13 Active	W/R
0840	8000 0840	8004 2000	Memory Parity Error Status	R	-	660
0842	8000 0842	8004 2002	L2 Error Status	R	-	660
0843	8000 0843	8004 2003	L2 Parity Read & Clear	R	-	660
0844	8000 0844	8004 2004	Unsupported Transfer Type Error	R	-	660
0850	8000 0850	8004 2010	I/O Map Type	W	-	660
0852	8000 0852	8004 2012	Board ID	R	-	logic	4
0860	8000 0860	8004 3000	Freeze Clock Reg Low	R/W	-	EPLD	11
0862	8000 0862	8004 3002	Freeze Clock Reg High	R/W	-	EPLD	11
0866	8000 0862		Processor 1 PD Register	R		logic
0867	8000 0867		Processor 2 PD Register	R		logic
0868	8000 0868		I2C Control Register	W/R		logic
086B	8000 086B		L2 Control Register	W/R		logic
0870	8000 0870		Processor Sequence Register	R		logic
0871	8000 0871		Processor Enable Register	W		logic
0880	8000 0880	8004 4000	SIMM Presence Detect Slot 1/2	R	-	logic	4
0881	8000 0881	8004 4001	SIMM Presence Detect Slot 3/4	R	-	logic	4
	8000 0CF8		PCI/BCR Configuration Address	R/W	-	660
	8000 0CFC		PCI/BCR Configuration Data	R/W	-	660
	8080 08xx		PCI Type 0 Configuration Addr	R/W	-	660
	8080 0800		Vendor Identification	R	-	SIO
	8080 0801		Vendor Identification	R	-	SIO
	8080 0802		Device Identification	R	-	SIO
	8080 0803		Device Identification	R	-	SIO
	8080 0804		Command	R/W	0F	SIO
	8080 0805		Command	R/W	00	SIO
	8080 0806		Device Status	R/W	-	SIO
	8080 0807		Device Status	R/W	-	SIO
	8080 0808		Revision Identification	R/W	-	SIO
	8080 0840		PCI Control	R/W	21	SIO
	8080 0841		PCI Arbiter Control	R/W	00	SIO
	8080 0842		PCI Arbiter Priority Control	R/W	04	SIO
	8080 0843		PCI Arbiter Priority Control Extension	R/W	00	SIO
	8080 0844		MEMCS# Control	R/W	00	SIO
	8080 0845		MEMCS# Bottom of Hole	R/W	10	SIO
	8080 0846		MEMCS# Top of Hole	R/W	0F	SIO
	8080 0847		MEMCS# Top of Memory	R/W	00	SIO
	8080 0848		ISA Address Decoder Control	R/W	F1	SIO
	8080 0849		ISA Address Decoder ROM Block	R/W	00	SIO
	8080 084A		ISA Address Bottom of Hole	R/W	10	SIO
	8080 084B		ISA Address Top of Hole	R/W	0F	SIO
	8080 084C		ISA Controller Recovery Timer	R/W	56	SIO
	8080 084D		ISA Clock Divisor	R/W	10	SIO
	8080 084E		Utility Bus Chip Select A	R/W	07	SIO
	8080 084F		Utility Bus Chip Select B	R/W	FF	SIO
	8080 0854		MEMCS# Attribute Register #1	R/W	-	SIO
	8080 0855		MEMCS# Attribute Register #2	R/W	-	SIO
	8080 0856		MEMCS# Attribute Register #3	R/W	-	SIO
	8080 0857		Scatter/Gather Relocation Base	R/W	-	SIO
	8080 0860		PIRQ Route Control 0	R/W	0F	SIO
	8080 0861		PIRQ Route Control 1	R/W	0F	SIO
	8080 0862		PIRQ Route Control 2	R/W	80	SIO
	8080 0863		PIRQ Route Control 3 (Unused)	R/W	80	SIO
	8080 0880		BIOS Timer Base Address	R/W	-	SIO
	8080 0881		BIOS Timer Base Address	R/W	-	SIO
	8080 10xx		PCI Type 0 Configuration Addr	R/W	-	660
	8080 20xx		PCI Type 0 Configuration Addr	R/W	-	660
	8080 40xx		PCI Type 0 Configuration Addr	R/W	-	660
	8080 80xx		PCI Type 0 Configuration Addr	R/W	-	660	11
	8081 00xx		PCI Type 0 Configuration Addr	R/W	-	660	11
	8082 00xx		PCI Type 0 Configuration Addr	R/W	-	660	11
	8084 00xx		PCI Type 0 Configuration Addr	R/W	-	660	11
	8088 00xx		PCI Type 0 Configuration Addr	R/W	-	660	11
	8090 00xx		PCI Type 0 Configuration Addr	R/W	-	660	11
	80A0 00xx		PCI Type 0 Configuration Addr	R/W	-	660	11
	80C0 00xx		PCI Type 0 Configuration Addr	R/W	-	660	11
	BFFF EFF0	BFFF EFF0	System Error Addr	R	-	660
	BFFF FFF0	BFFF FFF0	Interrupt Vector	R	-	660
	FFFF FFF0	FFFF FFF0	Flash Write Addr/Data	W	-	660
	FFFF FFF1	FFFF FFF1	Flash Lock Out	W	-	660
Notes: The first 5 hex digits in the contiguous and non-contiguous mode columns represent the memory page number for which the protection attributes may be set in contiguous I/O mode. That is, devices having the same first five digits in this column will have the same attributes in the memory page table. In the Set To column, a long dash - means that the initialization firmware does not write to this register. The register is either not used, not written to, or the value of it depends on changing circumstances. If the word Memory appears, please refer to the System Memory section of the 660 User's Manual. KBD = Keyboard/Mouse Controller RTC = Real Time Clock, also known as the TOD (Time Of Day clock) NVR = Non-Volatile RAM, in the same package as the RTC 660 = The 660 Bridge. The control signals for these ports are partially decoded by the SIO. The System I/O EPLD completes the decodes, and issues control signals to the registers, which are usually X-bus buffers. Port 94 may be used by a certain video controller (e.g., Weitekt 9100). The SIO chip positively decodes this port; therefore, bus contention may arise when both devices claim the PCI cycle to this port address. Bus contention results in invalid data and possible harm to the hardware. For best I/O protection in non-contiguous I/O mode, do not use these ports. These mix address es with other devices on the same page. Use of this address range is recommended. For best I/O protection in non-contiguous I/O mode, do not use these ports. These mix address es with other devices on the same page; however, media sense is not supported at the second ary address range. Ports 60, 92, 3F2, and 0F are partially contained in the CORAL chip. They are subtractively de coded in the CORAL chip. Set register 81C to C0h if an L2 is installed, else leave at reset value. Not used.