Section 1
Physical Design Guidelines

These guidelines are given to aid designers with the physical design phase of their PowerPC reference design board. The guidelines are not intended to replace good physical design practices for the signal types and frequencies discussed, but to supplement standard practice by pointing out sensitive and critical areas. Some discussion of the IBM implementation of the reference board is also included to establish the context for the wiring guidelines.

1.1 Motherboard Construction

The general construction of the PowerPC 604 SMP reference motherboard (motherboard) is shown in Figure 1. It is constructed with two high frequency signal layers in the center, two power planes, and two external general purpose signal layers.



A top view of a typical wiring channel, as implemented on the motherboard, is shown in Figure 2 (all dimensions are shown in inches). Minimum trace width is 0.004 in. (at 1:1), and minimum space width is 0.006 in. (at 1:1). For fabrication information, see Figure 3.



1.2 Riser Construction

The general construction of the PowerPC 604 SMP riser board (riser) is shown in Figure 4. It is constructed with two power planes in the center and two external signal layers.



A top view of a typical wiring channel, as implemented on the riser, is shown in Figure 5 (all dimensions are shown in inches). Minimum trace width is 0.006 in. (at 1:1), and minimum space width is 0.006 in. (at 1:1). For fabrication information, see Figure 6.



1.3 Cheetah3 Board Construction

The general construction of the PowerPC 604 SMP cheetah3 board (cheetah3) is shown in Figure 7. It is constructed with two voltage planes in the center, two signal layers, two ground planes, and two external signal layers.



A top view of a typical wiring channel, as implemented on the cheetah3, is shown in Figure 8 (all dimensions are shown in inches). Minimum trace width is 0.006 in. (at 1:1) and minimum space width is 0.006 in. (at 1:1). For fabrication information, see Figure 9.



1.4 General Wiring Guidelines

1. No wires are allowed to cross into the AUDIO sub-system unless they are connected to a device in that section.

2. All clock wires must have a minimum number of vias and be routed on internal planes.

3. If a wire is routed near a via that is part of a clock net, there must be at least one vacant wiring channel between the wire and the clock via.

4. No clock wires may be routed within one inch from the edge of the board.

5. A power (ground or voltage) plane split occurs where there is a discontinuity in the plane. As shown in Figure 10, route wires across splits in a power plane in the most perpendicular manner possible. Do not run wires parallel to the split in close proximity to the split.



6. I/O wires must be routed away from densly wired non-I/O wiring areas.

7. All I/O wires must be routed such that the 22pf shunt capacitor is the last thing on the net before the I/O connector itself.

8. Minimize the number of wires that cross under the MPC970 (U26) and the number of wires that cross under the AMCC (U30) PLL on the top surface. If a wire is routed near a via attached to a clock wire, it must have a vacant wiring channel next to it.

9. Critical nets (604 bus signals) must not be placed on outer plane, if possible.

10. 604 and PCI buses (except ISA and X-buses) must be wired point to point .

Several groups of nets require special attention. They are listed in Table 1 in the order of the importance for meeting their design rules. For example, ensuring that the clock nets are routed according to their design rules is more important than ensuring that the PCI bus nets are routed according to their design rules. The ideal system design will meet all of the suggested design rules, but this information is included to guide the designer in case some tradeoffs have to be evaluated.

Table 1. Order of Importance for Meeting Design Rules

Order of Importance

 Group
1

Clock Nets

2

CEC Critical Nets

3

L2 Critical Nets

4

PCI Critical Nets

5

PCI Address/Data Nets

6

Noise Sensitive Nets

7

Other Nets

1.5 Clock Wires

General requirements: See Table 2 for specific wiring length requirements.

1. Clock nets are the most critical wiring on the board. Their wiring requirements must be given priority over the requirements of other groups of signals.

2. Clock nets are to have a minimum number of vias.

3. No clock wires may be routed closer than one inch to the edge of the board.

4. Clock nets with more than two nodes (devices connected to them) are to be daisy-chained. Stubs and star fanouts are not allowed.

5. Clock nets are to be routed as much as possible on internal signal planes.

6. Where series termination resistors are required, place them as close as possible to the clock generator.

7. Route a ground trace as a shield in the adjacent wiring channel on both sides of the clock trace. Connect these shield traces to the ground plane using at least one via in each inch of trace. Completely surround the clock trace with shield traces.

8. Table 2 shows the length and tolerances of the clock nets. All dimensions are shown in inches. The Design Rule column shows the guideline, and the Reference Board column shows the actual length of the net on the reference board.

9. No more than one turning via for a total of three vias per net is allowed.

Table 2. Clock Wires

Net Name

 Length
SRAM_BCLK<3:0>

As short as possible. Define this clock length as L1 (Clock traces on SIMM must be 3.0 in. long).

MC_SRAM_BCLK0

As short as possible

MC_SRAM_BCLK1

As short as possible

MC_SRAM_BCLK2

As short as possible

MC_SRAM_BCLK3

As short as possible

TAG_BCLK

(L1 )  0.1 in.

MC_TAG_BCLK

As short as possible

PROC1_BCLK<2:0>

(L1 + 0.24 in.)  0.1 in. (Clock traces on processor card must be 2.76 in. long)

MC_PROC1_BCLK0

As short as possible

MC_PROC1_BCLK1

As short as possible

MC_PROC1_BCLK2

As short as possible

PROC2_BCLK<2:0>

(L1 + 0.24 in.)  0.1 in. (Clock traces on processor card must be 2.76 in. long)

MC_PROC2_BCLK0

As short as possible

MC_PROC2_BCLK1

As short as possible

MC_PROC2_BCLK2

As short as possible

663_BCLK

(L1 + 3.0 in.)  0.1 in.

MC_663_BCLK

As short as possible

664_BCLK

(L1 + 3.0 in.)  0.1 in.

MC_664_BCLK

As short as possible

4403_BCLK

(L1 + 3.0 in.)  0.1 in.

MC_4403_BCLK

As short as possible

MC_BCLK_SPARE

As short as possible

PAL_BCLK

(L1 + 3.0 in.)  0.1 in.

XTAL1_MPC970

As short as possible

XTAL2_MPC970

As short as possible

TTL_CLK

As short as possible

4403_FBCLK

As short as possible

4403_FBCLK_R

As short as possible

X2FOUT0

As short as possible

PLL_FOUT2

As short as possible

SLOT2_PCICLK

As short as possible (If using IBM Riser card 25JP-RISER3-A, clock trace on that riser is 3.73 in. long). Define this clock length as L2.

PLL_FOUT3

As short as possible

SLOT1_PCICLK

(L2 + 0.9 in.)  0.1 in. (If using IBM Riser card 25JP-RISER3-A, clock trace on that riser is 2.81 in. long)

PLL_FOUT2A

As short as possible

SCSI_PCICLK

(L2 + 6.23 in.)  0.1 in.
(6.23 in. comes from 2.5 in. of PCI option card clock length per PCI spec plus 3.73 in. of IBM 25JP-RISER3-A clock length of slot2)

PLL_FOUT3A

As short as possible

82376_PCICLK

(L2 + 6.23 in.)  0.1 in.

PLL_FOUT1A

As short as possible

ETHNT_PCICLK

(L2 + 6.23 in.)  0.1 in.

PLL_FOUT0A

As short as possible

664_PCICLK

(L2 + 6.23 in.)  0.1 in.

PLL_FOUT1

As short as possible

MPIC_PCICLK

(L2 + 6.23 in.)  0.1 in.

PLL_FOUT0

As short as possible

DPAL_PCICLK

(L2 + 6.23 in.)  0.1 in.

FPAL_PCICLK

(L2 + 6.23 in.)  0.1 in.

ISA_CLK

As short as possible

14.3181MHZ

As short as possible

OSC_14.3181MHZ

As short as possible

20.00MHz_XTAL1

As short as possible

20.00MHz_XTAL2

As short as possible

24MHZ_SUPERIO

As short as possible

XTAL1I_24.576MHZ

As short as possible

XTAL1O_24.576MHZ

As short as possible

XTAL1I_16.934MHZ

As short as possible

XTAL1O_16.934MHZ

As short as possible

XTALI_33.8688MHZ

As short as possible

XTALO_33.8688MHZ

As short as possible

1.843MHZ_PMAN_CLK

As short as possible

16_X1

As short as possible

16_X2

As short as possible

XTAL1_32.768KHZ

As short as possible

XTAL2_32.768KHZ

As short as possible

SCSI_40MHZ

As short as possible

OSC_40MHZ

As short as possible

XTAL1_12MHZ

As short as possible

XTAL2_12MHZ

As short as possible

TIMER2_OUT

As short as possible

1.6 Noise Sensitive Wires

1.6.1 To Be Run With Adjacent Grounds

Noise sensitive wires require a ground wire in each adjacent wiring channel. See Table 3 for net names and comments. Connect shield (ground) traces to the ground plane using at least one via in each inch of trace. Completely surround the clock trace with shield traces.

Table 3. Noise Sensitive Wires (Ground Wires Adjacent)

NET NAME

 COMMENT
-POWER_GOOD/RESET

-BUFF_POWER_GOOD/RESET

-HRESET_CPU1A

-HRESET_CPU1B

-HRESET_CPU2A

-HRESET_CPU2B

-SRESET_CPU1A

-SRESET_CPU1B

-SRESET_CPU2A

-SRESET_CPU2B

1.6.2 To Be Run With No Wires in Adjacent Channels

For each of the signals in Table 4, run either no trace or a ground trace in the adjacent channel on each side of the signal. If used, connect shield (ground) traces to the ground plane using at least one via in each inch of trace.

Table 4. Noise Sensitive Wires (No Wires Adjacent)

NET NAME

 COMMENT
-ISA_REFRESH

-PCI_SERR

-ISA_IOCHCK

ISA_AEN

ISA_BALE

-ISA_IOR

This also has other restrictions

-ISA_IOW

This also has other restrictions

-XIOR

-XIOW

ISA_IOCHRDY

-ISA_MEMCS16

-ISA_MEMR

-ISA_MEMW

-ISA_SBHE

-ISA_SMEMR

-ISA_SMEMW

-ISA_IOCS16

-ISA_MASTER

-ISA_0WS

-SCSI_ATN

This also has other restrictions

-SCSI_BSY

This also has other restrictions

-SCSI_ACK

This also has other restrictions

-SCSI_RESET

This also has other restrictions

-SCSI_MSG

This also has other restrictions

-SCSI_SEL

This also has other restrictions

-SCSI_CD

This also has other restrictions

-SCSI_REQ

This also has other restrictions

-SCSI_IO

This also has other restrictions

1.7 CEC Critical Wires

All CEC critical wires must be wired to be as short as possible (see Table 5).

Table 5. CEC Critical Wires

NET NAME

 COMMENT
-DBB

2.5 in. max

DBB_P1TR

As short as possible

-K_DBG

As short as possible

-DBG

5.5 in. max

-K_TA

As short as possible

-TA

5.5 in. max

-K_TEA

As short as possible

-TEA

5.5 in. max

-K_ARTRY

As short as possible

-ARTRY

5.5 in. max

-K_AACK

As short as possible

-AACK

5.5 in. max

-K_TA

As short as possible

-TA

5.5 in. max

-K_TS

As short as possible

-TS

5.5 in. max

-K_XATS

As short as possible

-XATS

5.5 in. max

-K_TBST

As short as possible

-TBST

5.5 in. max

TSIZ<2:0>

5.5 in. max

TT<4:0>

5.5 in. max

A_CPU1<31:0> (1)

See note (1) for route sequence; 2.5 in. max

A_CPU2<31:0> (1)

See note (1) for route sequence; 5.0 in. max

D_CPU1<63:0> (2)

See note (2) for route sequence; 3.6 in. max

D_CPU2<63:0> (2)

See note (2) for route sequence; 5.0 in. max

DP_CPU1<7:0> (3)

See note (3) for route sequence; 3.6 in. max

DP_CPU2<7:0> (3)

See note (3) for route sequence; 5.0 in. max

Notes:

  • Address routing sequence: U3 (82664)-J8 (processor slot 1)-series resistor-J9 (Processor slot 2)-J12 (SRAM+TRAM connector).
  • Data routing sequence: U4 (82663)-J8 (processor slot 1)-series resistor-J9 (Processor slot 2)-J12 (SRAM+TRAM connector).
  • Data parity routing sequence: U4 (82663)-J8 (processor slot 1)-series resistor-J9 (Processor slot 2)-J12 (SRAM+TRAM connector).

    • 1.8 L2 Cache Critical Wires

    All L2 control signals from U3 (82664) to J12 (SRAM + TRAM conn.) must be wired as short as possible. The wires shown in Table 6 are particularly critical.

    Table 6. L2 Critical Control Wires

    NET NAME

    		 COMMENT
    TAG_MATCH

    -SRAM_CNT_EN/ADDR1

    -SRAM_ADS/ADDR0

    1.9 PCI Critical Control Wires

    General requirements: PCI critical control wires are point to point. No stubs are desired, but if required, stubs must be less than 1.5 inches. All wires must be wired as short as possible. For net names and comments, see Table 7.

    Table 7. PCI Critical Control Wires

    NET NAME

    		 COMMENT
    -PCI_FRAME

    		J14 (PCI+ISA Dual Riser conn 25JP-RISER3-A) must be the last one on the net.

    -PCI_TRDY

    		J14 must be the last one on the net.

    -PCI_IRDY

    		J14 must be the last one on the net.

    -PCI_STOP

    		J14 must be the last one on the net.

    -PCI_DEVSEL

    		J14 must be the last one on the net.

    -PCI_C/BE<3:0>

    		J14 must be the last one on the net.

    1.10 PCI Address/Data Wires

    For comments and address routing sequence, see Table 8.

    Table 8. PCI Address/Data Wires

    NET NAME

    		 COMMENT
    PCI_AD<0:31>1

    		J14 must be the last one on the net.

    Note:

  • PCI Address/Data routing sequence: U4 (82664)-U3 (82663)-U32 (82376)-U10 (MPIC)-U12 (Am79C970)-U12 (NCR53C810)-M14 (Direct ROM)-J14 (Dual Riser 25JP-RISER3-A)

    • 1.11 SCSI I/O Wires

    SCSI I/O wires must be as short as possible. At least one wiring channel on either side of these wires must be free of wiring unless it is another I/O wire. These wires must run perpendicular to any non-I/O wires on opposite planes. These wires must be wired on internal planes as much as possible. For net names and comments, see Table 9.

    These wires must be wired in the following order: J32 (External SCSI)-U14 (SCSI Active Terminator)-U12 (Symbios 53C810)-J19 (Internal SCSI; unterminated).

    Table 9. SCSI I/O Wires

    NET NAME

    		 COMMENT
    SCSI_D<8:0>

    -SCSI_ATN

    -SCSI_BSY

    -SCSI_ACK

    -SCSI_RESET

    -SCSI_MSG

    -SCSI_SEL

    -SCSI_CD

    -SCSI_REQ

    -SCSI_IO

    1.12 Audio I/O Wires

    Audio I/O wires must be as short as possible. All of these wires must remain in the audio section. No wires are allowed to cross over (either completely or partially) the voltage divider around the audio section. For net names and comments, see Table 10.

    Table 10. Audio I/O Wires

    NET NAME

    		 COMMENT
    L_MIC

    R_MIC

    EXT_L_CD

    EXT_R_CD

    L_LINE

    R_LINE

    L_CD

    R_CD

    L_OUT

    R_OUT

    AUD_VREF

    AUD_REFFLT

    1.13 Input/Output Wires

    All of these wires must be as short as possible. At least one wiring channel on either side must be free of wiring unless it is another I/O wire. These wires must run perpendicular to any non-I/O wires on opposite planes. These wires must be wired on internal planes as much as possible. For net names and comments, see Table 11.

    Table 11. I/O Wires

    NET NAME

    		 COMMENT
    KYBD_DATA

    KYBD_DATA

    KYBD_CLK

    KYBD_CLK

    MOUSE_DATA

    MOUSE_DATA

    MOUSE_CLK

    MOUSE_CLK

    PARALLEL<16:0>

    -SOUT1

    -DTR1

    -RTS1

    -DCD1

    SIN1

    -DSR1

    -CTS1

    -RI1

    -SOUT2

    -DTR2

    -RTS2

    -DCD2

    SIN2

    -DSR2

    -CTS2

    -RI2

    -EXT_SOUT1

    -EXT_DTR1

    -EXT_RTS1

    -EXT_DCD1

    EXT_SIN1

    -EXT_DSR1

    -EXT_CTS1

    -EXT_RI1

    -EXT_SOUT2

    -EXT_DTR2

    -EXT_RTS2

    -EXT_DCD2

    EXT_SIN2

    -EXT_DSR2

    -EXT_CTS2

    -EXT_RI2

    1.14 Ethernet Wires

    Power and ground planes must be removed in the area of Twisted-Pair-Interface (C115, C114, T1, L3-4, L6-7, C575-576, C83, C91, & J21). This area must not have any other signal other than TXs & RXs passing by. For net names and comments, see Table 12.

    TPI signals (RXs and TXs) must have matched length.

    Table 12. TPI Wires

    NET NAME

    		 COMMENT
    TX+

    		Path: U2.95 - R10 - T1.1 and U2.94 - R98 - T1.1

    TX-

    		Path: U2.93 - R6 - T1.3 and U2.92 - R13 - T1.3

    RX

    		Path: U2.90 - T1.6 and U2.89 - T1.8

    TD+

    		Path: T1.16 - L7 - C83 - J21.1

    TD-

    		Path: T1.14 - L6 - J21.2

    RD+

    		Path: T1.11 - L4 - C91 - J21.3

    RD-

    		Path: T1.9 - L3 - J21.6

    1.15 Memory Wires

    General requirements: Memory wires must be wired as short as possible. For net names and comments, see Table 13.

    Table 13. Memory Wires

    NET NAME

    		 COMMENT
    KMA<11:0>

    		BUS GROUP

    MA_A<11:0>

    		BUS GROUP

    MA_B<11:0>

    		BUS GROUP

    MDP<7:0>

    -MRE<7:0>

    -MCE<7:0>

    MD<63:0>

    		BUS GROUP

    -KMWE0

    -MWE_A0

    -MWE_B0

    -KMWE1

    -MWE_A1

    -MWE_B1

    1.16 Battery Wires

    Battery connection to RTC (Signals BAT_PWR & VBAT) must be short and have 12-mil trace width.

    1.17 Fan Wires

    +12 volt traces to fans running at card edge must have 0.125 in. line width and must provide triple vias if required to change planes.

    1.18 8mm Tape Contents and Extract Instructions

    1.18.1 Download Instructions

    The enclosed 8mm tape was created using the tar command. First find the address of the 8mm tape drive by executing the following command:

    isdev -C -c tape.

    Then change the block size to 1024 by executing the following command:

    chdev -l rmt0 -a block_size=1024

    To extract the data, create a directory and ensure that at least 80M of free space is available. Use the cd command to get to the created directory and type the following:

    tar -xvf/dev/rmt0

    1.18.2 Cadence Version

    S Concept=version 1.7-S1

    S Allegro=version 11.0 or later

    S packagerXL

    1.18.3 Tape Contents

    The tape contains the following directories:

    PXL

    S Pst.* files, packager files

    S *View* files, Allegro feedback files

    S bom.* files, bill of material files

    Flatlab

    S Logic models used for this design

    (604 SMP Reference Board)

    S Schematic data

    S Postscript plots Each page=plot.* total=*.ps

    tscr

    S Cross reference sheets.