This document provides a detailed technical description of the PowerPCt 604 SMP
Reference Design, and is intended to be used by hardware, software, test, simulation, and
other engineers as a first source of information. Software developers should read through
the entire document because pertinent facts may be located in hardware sections.
The focus of this document is mainly on the motherboard electronics and firmware. Where
appropriate, this document references detailed information found in other documents.
Consult other documents for information on specific I/O devices (such as hard files,
CD-ROMs, L2 cache cards, video cards, etc.) that comprise a total system.
Recommendations for memory mappings, software implementations, and the like are only
recommendations and may or may not represent the algorithms implemented in boot code
or operating systems.
1.1 IBM Reference Products
IBM offers several different PowerPC reference products for a given PowerPC system.
1.1.1 Reference Design
The PowerPC 604 SMP Reference Design (reference design) is composed of both the
intangible design and the documentation describing that design. The reference design
documentation addresses the motherboard electronics, firmware, and various system
related issues. The reference design is composed of this Technical Specification and,
optionally, Gerber format physical design files on an 8mm tape, electrical device model files
in Cadencet format, system firmware guidelines, and contact information for commented
boot ROM source code. This is the only component of the reference product array that IBM
will offer for the PowerPC 604 SMP Reference Design.
1.1.2 Reference Boards and Systems
The PowerPC 604 SMP Reference Board (reference board) is the physical implementation
of the motherboard part of the reference design. The PowerPC 604 SMP Reference
System (reference system) consists of a complete 604 PowerPC computer system. IBM
will not offer PowerPC 604 SMP reference boards or reference systems for sale. Instead,
IBM has enabled other vendors to design and manufacture boards and systems based on
the reference design. Contact your IMD Field Marketing Representative for further
information.
1.1.3 Reference Firmware
The PowerPC 604 SMP Reference Firmware (reference firmware) is described in the
reference design. It consists of the commented source code of the software contained in
the boot ROM. This is available from IBM as discussed in the Firmware section.
1.2 Purpose
The reference design is intended to help companies develop their own products using the
PowerPC architecture. The reference design may be used:
- As a baseline system in order to gauge the effects of changes on the design
- To test new boot code
- To test operating systems and/or applications
- For performance measuring.
The reference board is:
- Produced for internal use only, primarily to verify the design.
- A compliant implementation of the PowerPC Hardware Reference Platform
Specification, version 1.1
- Tested for functionality to the level of software available at the time of shipping
- A prototype of a system under development which may have prototype ASICs,
errata, and/or wiring changes.
The reference design is not:
- Offered for sale by IBM.
- A complete market ready design
- Tested for compliance to FCC and other regulatory requirements.
1.3 Differences Between Releases 1.0, 3.0, and 4.0
Release 1.0 of the reference design was preliminary, corresponds to pass 2 of the mother
board, and uses a preliminary version of the IBM27-82660. There is no release 2.0 of the
reference design.
Release 3.0 describes pass 3 of the mother board, and includes the Cheetah1 CPU card.
It incorporates the workarounds that were required for the errata found on release 1.0, and
also features the production release of the IBM27-82660. Also see the Errata section.
Release 4.0 also corresponds to pass 3 of the mother board, and includes the new
Cheetah3 CPU card. Minor corrections have been made to the body of the document.
1.4 Reference Design Overview
This section contains an overview of the reference design. The block diagram of the
reference design is shown in Figure 1 and Figure 2.
The reference design is compliant with the PowerPC Reference Platform Specification
Versions 1.0 and 1.1. It is also complaint with the PCI Local Bus Specification, revisions
2.0 and 2.1.
The reference design is a PowerPC based Symmetrical Multi-Processor (SMP)
system using the PowerPC 604 RISC microprocessor and the IBM27-82660 Bridge
chipset (660 Bridge). The core of the system is the Central Electronics Complex
(CEC) consisting of 1 or 2 CPU daughter cards and a Tag/SRAM daughter card,
which is used with the imbedded L2 controller in the 660 Bridge. With these
daughter cards, a variety of CEC configurations can be achieved.
The CEC is connected to main memory through the 660 Bridge. All I/O expansion
is connected to the CEC through the PCI bus from the 660 Bridge. PCI I/O
expansion includes imbedded SCSI HDD and Ethernet controllers, as well as two
PCI expansion slots on an LPX riser card. Further I/O expansion is provided via the
ISA and XBUS, which are derived from the PCI bus via a PCI/ISA bridge.
Imbedded ISA devices include Business Audio and standard PC for Serial, Parallel,
and FDD controllers. Two ISA expansion slots are available on the LPX riser slot.
XBUS I/O includes these other standard PC functions: Keyboard, Mouse, NVRAM,
and RTC (see Figure 2).
System firmware is provided in a FLASH or EPROM device accessed by the 664
via the PCI A/D lines. The 660 bridge direct ROM access does not conform to or
violate the PCI protocol because the PCI control signals remain inactive.
The 604 SMP is designed to an industry standard LPX (9" by 13") outline. Both
3.3v and +5v are required to power most system components. Components that
require +3.3v are supported by an additional output connector from a +3.3v power
supply. +3.6v is provided to the CPU slots by a 5v to 3.6v regulator on the
motherboard. +12v and -12v are required to support some of the peripheral
features. -5v is supplied only to the ISA connectors (via the riser card).
1.4.1 Processor Cards
The reference motherboard has two 256 pin DIMM connectors for the attachment of
daughter cards which provide the 604 microprocessor(s) for the system. These
cards interface with the motherboard over a 60x compliant bus having sideband
signals for power, resets, interrupts, L2 control, and card ID information.
1.4.2 Other CEC Functions
The reference design provides CPU bus clocks to the CEC at one of two bus frequencies
(nominally 60 MHz or 66 MHz as optimized for the installed processor cards). In general,
the processors on the daughter cards are capable of running their internal clocks at several
different multiples of the bus clock frequency. The reference design runs the PCI bus clock
at a fixed frequency multiple of one half the CPU bus clock frequency.
Consult your IBM representative for currently available choices of CPU types and operating
frequencies.
The reference design is equipped with an interface to support RISCWatch debugging and
monitor systems for PowerPC processors.
1.4.3 IBM27-82660 Bridge
The IBM27-82660 Bridge chipset supplies many of the functions of the reference design.
The 660 Bridge interfaces the CPU to system memory, the PCI bus, the L2 TAG and
SRAMS, the FLASH/ROM, and other reference design components.
1.4.4 L2 Cache
The reference design supplies an L2 cache controller, located inside the 660 Bridge
chipset. The motherboard provides a slot for an TAG/SRAM module. The 660 L2 is a
unified, write-through, direct-mapped, look-aside cache that supports 256K-1M of async
or sync SRAM to cache the low 1G of CPU memory space. The 660 L2 supplies data to
the CPU bus on write hits, and it snarfs the data (updates the SRAM data while the memory
controller is accessing DRAM memory) on read/write misses. It snoops PCI to memory
transactions. Typical read performance is 3-1-1-1, followed by -2-1-1-1 on pipelined reads.
1.4.5 System Memory
The reference design memory subsystem can support up to 256M of 70ns or faster DRAM
memory on eight 72 pin, DRAM (SIMM) modules via sockets. Each SIMM socket can
support a 4M, 8M, 16M or 32M, 72 pin SIMM with parity. The DRAM subsystem is 72 bits
wide: 64 data bits and eight parity bits. One parity bit is generated for each byte of data
written. The 660 Bridge can also be configured to perform ECC memory data checking and
correction using standard parity DRAM modules. The 660 Bridge also provides DRAM
refresh, and it supports EDO hyper-page mode DRAM.
Memory access performance from the CPU bus at 66MHz with 70ns DRAM is typically:
- Pipelined burst read: 5-4-4-4 CPU bus clocks-16 CPU clocks for 32 bytes of data
- Pipelined burst write: 3-3-4-4 CPU bus clocks-17 CPU clocks for 32 bytes of data.
Memory access performance from the PCI bus at 33MHz with 70ns DRAM is typically:
- Read bursts 5-1-1-1 -1-1-1-1 6-1-1-1 -1-1-1-1 6-1-1-1 -1-1-1-1 ... 6-1-1-1 -1-1-1-1
- Write bursts 5-1-1-1 -1-1-1-1 3-1-1-1 -1-1-1-1 3-1-1-1 -1-1-1-1 ... 3-1-1-1 -1-1-1-1.
1.4.6 PCI Bus
The 660 Bridge includes the interface between the PCI bus and the rest of the system. The
reference design allows CPU to PCI access and PCI bus master to memory access (with
snooping), and it handles all PCI related system memory cache coherency issues. Two PCI
expansion slots are provided.
The reference design also supports memory block locking, types 0 and 1 configuration
cycles, and ISA master access to system memory through the ISA bridge.
1.4.7 SCSI Controller
The Symbiost 53C810 controller attaches directly to the PCI bus on the
motherboard and supports the following features:
- Eight-bit SCSI-2 interface
- Variable block size and scatter/gather data transfers
- 32-bit word data bursts with variable burst lengths
- Full 32-bit PCI bus master
- 64-byte FIFO buffer.
1.4.8 Network Support AMD AM79C970A (Ethernet)
This component attaches to the PCI bus on the motherboard and supports the
following features:
- ISO8802-3 (IEEE/ANSI 802.3) and Ethernet Standards
- Big endian byte alignment
- Integrated Manchester Encoder-Decoder, integrated AUI and 10-base-T
transceiver
- Compliant to PCI 2.0
- 136 byte/128 byte transmit/receive FIFO.
This chip is connected to an RJ-45 connector on the motherboard for 10-base-T
Ethernet support.
1.4.9 Multi-Processor Interrupt Controller (MPIC)
This component attaches to the PCI bus on the motherboard and supports the
following features:
- 15 individual interrupt inputs with programmable edge or level polarity
- ISA compatible interrupt handling via external 8259 cascaded on INT0
- Distribution of interrupts for symmetric multi-processing (SMP) systems
- One to four processors with interrupts and soft reset functions
- Implementation of OpenPIC IC
- Selectable interrupt vector, priority, level, and routing software
- integrated 32 bit counters.
1.4.10 Flash ROM
The reference design uses an AMD AM29F040-120 Flasht ROM to contain the POST and
boot code. It is recommended that vital product data such as the motherboard speed and
native I/O complement be programmed into this device. It is possible to program the Flash
ROM before or during or after the motherboard manufacturing process.
After power on, the initial code that is fetched is supplied from this device. The 660 Bridge
manages ROM access and control. The reference design supports a 512K Flash ROM.
1.4.11 PCI/ISA Bridge Chip
This device(the Intel 82378ZB SIO) provides the PCI bus arbiter, a PCI to ISA bus
bridge, and system services such as DMA and interrupt control. Its major functions
are listed below:
- PCI bus arbiter
- Bridge between PCI and ISA
Supports 8/16 bit ISA devices
Addresses 24 bit on ISA
Partially decodes native I/O addresses
Forwards unclaimed PCI memory address below 16MB to the ISA bus
Forwards unclaimed PCI I/O address below 64KB to the ISA bus
Powers up to an "open" condition (cycles may be passed to the ISA bus)
Generates ISA clock with a programmable divide ratio of three or four
Allows ISA mastering and has programmable decodes which map ISA memory
cycles to the PCI bus
Has a 32-bit posted memory write data buffer (has no I/O buffering)
- Seven channel DMA controller
Has the function of two 83C37s with 32-bit extensions
Supports 8-bit or 16-bit devices on the ISA bus
Supports 32-bit addressing for ISA to PCI memory transfers
Has an 8-byte bidirectional buffer for DMA data.
- Timer block (function of 82C54 or block with the function)
- Interrupt Controller (function of two 8259s)
- Functions as PCI slave during programming and ISA slave cycles
- Functions as bus master during DMA or ISA master cycles.
1.4.12 Business Audio
Business audio is provided through the Crystal Semiconductort CS4232-KS EP stereo
audio chip. Conventional (Timer 2) PC speaker functions are also provided (both the Timer
2 signal from the SIO, and the audio chip, drive the speaker).
The system provides for stereo capture and playback. It can play MIDI files, but it is not a
full-functioned MIDI system. It has separate DMA channels for record and playback. The
system is processor driven and does not include a DSP. Compression and decompression
are supported in the hardware. The audio output is to a single speaker mounted in the
cabinet. Also supported are four rear-mounted 3.5 mm jacks for:
- Stereo earphones
- Stereo microphone input
- Stereo line in
- Stereo line out.
There are also motherboard connectors for direct playback from the CD-ROM and for an
internal fax-modem card.
1.4.13 Native I/O Controller National PC87332 Super I/O
This component is located on the ISA bus and contains:
- Floppy Disk Controller (software compatible with DP8473,765A and NS82077)
- Two serial ports (software compatible with INS8250N-B, PC16550A, and PC16450.
Has FIFOs. Decodes COM 1-4)
- One enhanced bidirectional parallel port
- IDE interface (unused).
1.4.14 X Bus
The ISA/XBUS bridge function is supported by the ISA bridge and other devices.
1.4.15 Time of Day Clock
The reference design uses a Dallas Semiconductort DS1385S to provide the real time
clock (TOD or RTC) function. This device is PC compatible and resides on the X-bus. It
features an additional 4K of NVRAM and a replaceable battery.
1.4.16 PS/2 Compatible Keyboard/Mouse Controller
The reference design uses an Intel 8042AH as a keyboard and mouse controller.
The code used is the same version as used in IBM Personal System/2 machines. This
microcode may differ from other 8042 type keyboard controllers.
1.4.17 System I/O EPLD
The system I/O EPLD is a programmable logic device that uses the X-bus signals and the
partial decode signals from the SIO to decode chip selects for various components. It
contains several system planar registers and glue logic for planar subsystems.
1.4.18 System Clocks
The motherboard clocks are provided by two PLL crystals and oscillators. The master PLL
provides all the CPU bus clocks from one of two reference sources. At the CPU bus
frequency, it also provides a seed clock to the second PLL, which generates the PCI bus
clocks. One of the PCI clocks is used by the PCI to ISA bridge controller to generate the
ISA bus clock and timings.
I/O clocks (keyboard, mouse, 82376/82378ZB timers, SCSI, etc.) are provided by
crystal and oscillators on the motherboard and are located near the intended load.
The reference design is intended for typical PC peripherals. Products from a large number
of manufacturers should work satisfactorily. Reference boards do not come with all of the
required peripherals, cables, speaker, indicator LEDs, switches, and such that are needed
to configure a properly working system.
Table 1 outlines the generic requirements for peripherals and gives examples of some
devices that have been used for testing. It is not a recommendation of any particular
vendor. The purpose of this table is to outline at least one set of peripherals that may be
used to begin testing.
Table 1 does not include cables for a parallel port, indicators, a switch, or a speaker.
An IBM 3101 asynchronous terminal or equivalent is required for testing with the bring up
driver (BUD) code. Settings are 8-bit, no parity, one stop bit, and 9600 baud. VT100 or VT52
emulator terminals may be acceptable. It is desirable to also have a video monitor for BUD
tests. The boot code will boot with either an async console, a video on motherboard, or
both.
| Table 1. Quickstart Peripheral List
|
| Generic Description
|
Example Device
|
| L2 TAG/SRAM card, 512KB
|
IBM Corp. P.N. 26H3015
|
| Memory SIMMs 16MB
|
Hitachi HB56D436B-7, IBM 57G8901
|
| Video adapter card, PCI S3
|
Diamond Stealth (S3) 864
|
| Floppy disk drive, 3.5"x1.44MB
|
Alps DFR723F, IBM 73G4514, Mitsubishi MF355F-258UG
|
| Hard disk drive, SCSI-2, 8 bit
|
Quantum LPS270/5405, Maxtor MXT-540SL, IBM WDS-3200
(79F4042)
|
| Hard disk drive, SCSI 1GB
|
IBM 94G3187
|
| CD_ROM drive, internal SCSI
|
Toshiba XM-4101BMY
|
| CD_ROM drive, internal SCSI, 4x
|
Toshiba 5301-4x
|
| Chassis, LPX
|
Olsen Metal Products
|
| Power supply, 200W Energy Star
|
API-3186S, IBM 06H2968
|
| Switch ( Power ON/OFF )
|
IBM 06H3860
|
| Box fan
|
Panaflow FBA08T12M
|
| Box fan shock mounts
|
IBM 81F7977
|
| Internal cables, floppy, SCSI, and
CD-ROM
|
Standard cables
|
| Speaker, internal 8W .5W 2pin
|
|
| LED, 2.5 ma drive
|
|
| Asynchronous terminal
|
IBM 3101
|
| Super VGA monitor
|
IBM 6324, 6325, 6327, 9524, 9525, 9527, 9521
|
| Keyboard, PS/2 compatible
|
|
| Mouse, PS/2 compatible
|
|
