Section 1
CPU Card

The IBM PowerPC CPU Card (Cheetah3) is a PowerPC CPU card for the reference design motherboard (see Figure 1). One Cheetah3 can be used for a uniprocessor system and two cards can be used for a 2-way SMP system. The card is designed to meet the electrical, physical, and thermal requirements of the motherboard with the following performance and features:

Up to 66MHz system bus speed
One PowerPC CPU with fansink
Up to 132MHz (604) operation with the specified power supplies and cooling
Contains power supply support for possible future lower voltage CPUs.

Cheetah3 can be used with the 603e, 603ev, 604, and 604ev CPUs. See the Bills of Materials section and the Schematics section for different Cheetah3 card configurations for the above processors. Except as noted, the information in this section applies to all CPU versions of Cheetah3.

Cheetah3 interfaces to the reference design motherboard through the CPU slot connector, which is a 256-pin card edge connector. Cheetah3 schematics are located in the Schematics section.

1.1 Major Components

1.1.1 PowerPC Processor

The CPU card uses a PowerPC 603e, 603ev, 604, or 604ev CPU in a Ball Grid Array package.

603e refers to an improved, 3.3v version of the 603.
603ev refers to an improved 2.5/3.3v version of the 603e.
604ev refers to an improved, 2.5/3.3v version of the the 604.

The PPC CPUs use an advanced 3.3v (or 2.5/3.3v) CMOS technology and are fully I/O compatible with TTL devices. The reference design allows the Cheetah3 CPU to run at bus speeds of 60MHz and 66MHz using the current fansink and power supplies.

As shown on the Cheetah3 schematics, most of the CPU I/Os exit Cheetah3 to the reference design motherboard via the CPU slot connector.

1.1.2 JTAG/RISCWatch Interface

Refer to the appropriate 60x User's Manual and RISCWatch documentation for information on the RISCWatch/ESP facility. Refer to the Cheetah3 schematics in the Schematics section for specifics of the interconnection between the CPU and the RISCWatch connector. The RISCWatch signals exit Cheetah3 via the CPU slot connector.

1.1.3 J2 Auxiliary Test Connector

J2 provides access to some of the signals on the CPU bus interface for debug purposes. IBM makes no recommendation as to the use of this connector. J2 is a 2x7 header on 0.1 inch centers (see Figure 2). Table 1 shows the pinout of J2.

Table 1. J2 Aux Connector Pinout

Pin No.

Signal Name

1

SYS_BR#

2

TC2

3

TC1

4

TC0

5

BG#

6

nc

7

RSRV#

Pin No.

Signal Name

8

SRESET_A#

9

nc

10

HRESET_A#

11

INT_A#

12

DPE#

13

APE#

14

GND

1.1.4 Fansink

The 604 processor on Cheetah3 requires a fansink to ensure proper cooling under worst case conditions in the reference system. As shown in Figure 3, the fansink is held to the CPU with a spring clip mounted to the Cheetah3 circuit board by a pair of standoffs. A piece of Thermostratet thermal tape is used to thermally connect the fansink to the chip package. The tape also allows for vibration and for non-parallelism between the sink and the chip package.

The fansink requires +12v, which is provided via a 2 wire cable (see Figure 4) which has a 3 position connector attached. The connector attaches to a 3 pin (0.1 in. centers) header on the motherboard. It is recommended that the motherboard header connect both pin 1 and pin 3 to ground to allow the connector to function properly in either orientation.

The spring clip is manufactured by A. K. Stamping (908) 232 - 7300. Their part number is 83866072.

1.2 Configuration Options

Cheetah3 is equipped with several jumper and pop/no-pop (either populate or not populate the component) options to increase the flexibility of the card.

1.2.1 Bus Clock Skew Circuit

604_SYSCLK, the CPU bus clock supplied by the motherboard, can be configured for minimum clock skew or for a forced 1ns delay. This can sometimes be useful when matching the timing characteristics of a given CPU card to those of the motherboard. Cheetah3 is supplied with the delay activated (0W resistors installed for R22 and R26, and R12 not populated). The delay can be taken out of the clock line by removing R22 and R26, and installing a 0W resistor in R12.

The delay element is a trace that is about 5 inches long.

1.2.2 2.5v Power Supply

Cheetah3 is designed to support the 60x ev series, which require a 2.5v core logic power supply. Cheetah3 generates a 2.5v power supply from the 3.3v power supply. See the Schematics section for details.

1.2.3 Presence Detect Bits

The presence detect bits PD[0:3] on Cheetah3 tell the motherboard the speed capability of the CPU on the card. The motherboard detects the speed capability of each of the CPU cards in the system. It then sets the operating frequency of the CPU bus clock supplied to each CPU card. The motherboard then sets the value of the PLL configuration bits PLL_CFG[0:3] by driving FREQ_ID[0:3] to the appropriate levels.

PD[0:3] are pulled up by 10kW resistors on the motherboard. To assert a logic 0, the CPU card pulls the signal low with a 100 ohm resistor. Cheetah3 uses R40, R41, R42, and R43 to set the value of the PD bits. See the Schematics section for details.

1.2.4 DRVMOD Bits

The DRVMOD[0:1] inputs to the 604 control certain of the 604 output driver characteristics. The value of these bits is set by the motherboard using DRVMOD[0:1], which are pulled up on Cheetah3 by a pair of 10kW resistors.

1.2.5 Additional Bits

The spare PAL site U2 is not populated or supported.

SYS_DBWO# and APE# are pulled up with a 10k resistor because they are not driven by the motherboard.

LSSD#, L1_TEST_CLK, L2_TEST_CLK, and ARRAY_WR are each pulled up with a 10k resistor as recommended by the 604 User's Manual.

L2_INT is pulled down with a 1kW resistor as per the 604 User's Manual.

AVDD is connected as shown to increase the noise immunity of the 604 PLL by decoupling the PLL supply.

R46 and R47 are supplied to allow the heatsink to be grounded for EMC purposes.

1.3 Electrical and Thermal Requirements

1.3.1 Absolute Maximum Ratings

Table 2. Voltage Ratings
	Parameter1	Min.	Max.	Unit
VDD	3.3v Supply Voltage	-0.3	3.6	v
VCC	5.0v Supply Voltage	-0.3	7.0	v
VIN	Input Voltage	-0.3	5.5	v2
TJCPU	Processor Junction Temperature	0	105	5C
TSTG	Storage temperature range	-55	150	5C
Notes: 1. Absolute Maximum ratings are stress ratings only, functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent dam age to the devices on the card. 2. PowerPC 604 processor additionally requires that no Input exceed the 3.3v supply voltage by more than 2.5v during power-on reset.

1.3.2 DC Specifications

Table 3. DC Recommended Operating Conditions
	Parameter	Min.	Max.	Unit
VIN	Input High Voltage	2.0	5.5	v1
VIL	Input Low Voltage	0.0	0.8	v
CVIH	BUS_CLK Input High Voltage	2.4	5.5	v
CVIL	BUS_CLK Input Low Voltage	0.0	0.4	v
IIH	Input High Current		100	uA
IIL	Input Low Current		100	uA
VOH	Output High Voltage IOH = -18mA	2.4	3.78	v1
VOL	Output Low Voltage IOL = 14mA	0.0	0.4	v
VDD5.0	5v Power Supply Voltage	4.5	5.5	v
IDD5.0	5v Power Supply Current		0	A
VDD3.3	VDD Power Supply Voltage	3.0	3.6	v
IDD3.3	VDD Power Supply Current		5.6	A
V12	12v Power Supply Voltage	10.8	13.2	v
I12	12v Power Supply Current		.1	A2
Notes: 1. All CPU bus receivers on Cheetah3 are 5.0v tolerant. 2. The CPU fansink requires 12v from a connector on the motherboard.

1.3.3 Thermal

Table 4. Thermal Recommended Operating Conditions
	Parameter	Min.	Max.	Unit
TJCPU	Processor Junction Temperature	0	101	5C
	Airflow1	150	-	lfpm
TAMB	Ambient Temperature at Leading Edge of Card		34	5C
Notes: 1. This air velocity is required at the pass transistor (if installed) and at the CPU heatsink (or fansink).

1.3.4 AC Timing Requirements

Table 5. AC Timing Recommended Operating Conditions
Symbol	Parameter	1nS Skew		No Skew	UNIT
Symbol	Parameter	Min.	Max.	Min.	Max.
FCPU	CPU max frequency 2		132		132	MHz
FBUS	BUS_CLK Frequency 2	50.0	66.6	50.0	66.6	MHz
TCYC	BUS_CLK cycle time at 1.5v	15	20	15	20	nS
Clock	BUS_CLK(n) Duty Cycle	40	60	40	60	%
	BUS_CLK(n) Clock Trace Length	8.65	8.85	3.65	3.85	inches3
	BUS_CLK(n) Clock Net Loading		10		10	pF
Notes: 1. All timings are derived from the PowerPC 604 timing specifications for a 66.67MHz bus device with a 2:1 CPU to SYSCLK ratio. Timings are measured at the CPU on Cheetah3 and and are given as rela tive to the SYSCLK input on the CPU. Where conflicts exist, the PowerPC 604 Hardware Specification supersedes this document. 2. CPU and bus frequency are set by the motherboard logic as a function of the capabilities of the CPU cards that are installed in the system. See the Clocks section. 3. Wire each BUS_CLK(n) point to point between J1 and a single load at the trace length specified. This will match this net to the other clock nets on the CPU bus. 4. Critical nets should be wired point to point. These nets are: TS#, TA#, TBST#, TSIZ(0..2), TT(0..4), DPE#, ABB#, AACK#, ARTRY#, DRTRY#, DBB#, DBG#, BG#. BR#, GBL#, SHD#, DP(0..7)#, A(0..31), DL(0..31), DH(0..31).

1.4 Electrical Model of Major Signal Groups

The physical signal paths (traces) of some major signal groups are modeled in Figure 5, where:

indicates a trace length that is modeled as a transmission line, where Zo = 70W Characteristic Impedance,
TD = 177ps/in Time Delay, and
RS = 159mW/in DC Resistance.
L gives the maximum length of the trace in inches. For critical nets, L must be less than or equal to three inches. The critical nets are: TS#, TA#, TBST#, TSIZ[0:2], TT[0:4], DPE#, ABB#, AACK#, ARTRY#, DRTRY#, DBB#, DBG#, BG#. BR#, GBL#, SHD#, DP[0:7]#, A[0:31], DL[0:31], DH[0:31].

1.5 CPU Card Slot Connector

Cheetah3 connects to the reference design motherboard mainly through the CPU card connector, J1 (see Figure 6). The pinout of J1 is shown in Table 6. The signal descriptions are shown in the CPU Bus section.

1.5.1 Pin Definitions

Table 6. CPU Card Pin List

PIN#	SIGNAL NAME	TYPE
1	GND
2	DRVMOD0	I
3	PD0	O
4	PD2	O
5	GND
6	SYS_DATA_H[30]	I/O
7	3.6v/3.3v	Unused
8	SYS_DATA_H[28]	I/O
9	SYS_DATA_H[26]	I/O
10	SYS_DATA_H[24]	I/O
11	GND
12	SYS_DATA_H[22]	I/O
13	SYS_DATA_H[20]	I/O
14	SYS_DATA_H[19]	I/O
15	SYS_DATA_H[17]	I/O
16	SYS_DATA_H[15]	I/O
17	GND
18	3.6v/3.3v	Unused
19	SYS_DATA_H[12]	I/O
20	SYS_DATA_H[11]	I/O
21	SYS_DATA_H[9]	I/O
22	SYS_DATA_H[7]	I/O
23	GND
24	SYS_DATA_H[5]	I/O
25	SYS_DATA_H[3]	I/O
26	SYS_DATA_H[2]	I/O
27	SYS_DATA_H[0]	I/O
28	GND
PIN#	SIGNAL NAME	TYPE
29	3.3v
30	3.3v
31	SYS_DATA_L[28]	I/O
32	SYS_DATA_L[26]	I/O
33	SYS_DATA_L[24]	I/O
34	GND
35	SYS_DATA_L[22]	I/O
36	3.3v
37	SYS_DATA_L[20]	I/O
38	SYS_DATA_L[18]	I/O
39	SYS_DATA_L[16]	I/O
40	SYS_DATA_L[14]	I/O
41	GND
42	3.3v
43	SYS_DATA_L[12]	I/O
44	SYS_DATA_L[11]	I/O
45	SYS_DATA_L[9]	I/O
46	SYS_DATA_L[7]	I/O
47	GND
48	3.3v
49	SYS_DATA_L[4]	I/O
50	SYS_DATA_L[3]	I/O
51	SYS_DATA_L[1]	I/O
52	SYS_DATA_L[0]	I/O
53	SYS_DP5	I/O
54	3.3v
55	3.3v
56	SYS_DP2	I/O
PIN#	SIGNAL NAME	TYPE
57	SYS_DP0	I/O
58	GND
59	BUS_CLK2	Unused
60	GND
61	SYS_ADDR[29]	I/O
62	SYS_ADDR[28]	I/O
63	SYS_ADDR[26]	I/O
64	SYS_ADDR[25]	I/O
65	SYS_ADDR[23]	I/O
66	SYS_ADDR[21]	I/O
67	GND
68	DRTRY#	I/O
69	GND
70	SYS_ADDR[19]	I/O
71	3.3v
72	SYS_ADDR[17]	I/O
73	GND
74	SYS_ADDR[13]	I/O
75	SYS_ADDR[12]	I/O
76	SYS_ADDR[11]	I/O
77	SYS_ADDR[9]	I/O
78	GND
79	SYS_ADDR[7]	I/O
80	SYS_ADDR[5]	I/O
81	SYS_ADDR[3]	I/O
82	3.3v
83	SYS_ADDR[0]	I/O
84	3.3v
85	GND
86	SYS_AACK#	I
87	GND
88	SYS_DATA_BUS_GR#	I
89	SYS_TA#	I
90	SYS_DBB#	I
91	SYS_TEA#	I
92	+5v
93	GND
94	XATS#	I/O
95	SYS_WT#	I/O
96	SYS_TT[1]	I/O
97	SYS_ARTRY#	I/O
98	SYS_SHARED#	I/O
99	GND
100	+5v	I/O
PIN#	SIGNAL NAME	TYPE
101	SYS_ABB#	I/O
102	+5v
103	SYS_TT[2]	I/O
104	GND
105	TCK	I
106	TDI	I
107	SRESET_A#	I
108	L2_AACK_EN#	Unused
109	CONFIG#	Unused
110	GND
111	TRST#	I
112	+5v
113	HALT_A/QREQ_A	O
114	L2_WT#	Unused
115	RUN/QAK	I
116	GND
117	+5v
118	SYS_ADDRP[0]	I/O
119	GND
120	SYS_ADDRP[1]	I/O
121	VREF
122	L2_BR#	Unused
123	L2_CLAIM#	Unused
124	L2_CLR#	Unused
125	PWR_DWN	I
126	FREQ_ID0	I
127	FREQ_ID2	I
128	GND
129	DRVMOD1	I
130	GND
131	PD1	O
132	PD3	O
133	SYS_DATA_H[31]	I/O
134	SYS_DATA_H[29]	I/O
135	GND
136	SYS_DATA_H[27]	I/O
137	SYS_DATA_H[25]	I/O
138	SYS_DATA_H[23]	I/O
139	3.6v/3.3v	Unused
140	SYS_DATA_H[21]	I/O
141	GND
142	SYS_DATA_H[18]	I/O
143	SYS_DATA_H[16]	I/O
144	SYS_DATA_H[14]	I/O
PIN#	SIGNAL NAME	TYPE
145	SYS_DATA_H[13]	I/O
146	3.6v/3.3v	Unused
147	GND
148	SYS_DATA_H[10]	I/O
149	SYS_DATA_H[8]	I/O
150	SYS_DATA_H[6]	I/O
151	3.3v
152	SYS_DATA_H[4]	I/O
153	GND
154	SYS_DATA_H[1]	I/O
155	SYS_DATA_L[31]	I/O
156	SYS_DATA_L[30]	I/O
157	SYS_DATA_L[29]	I/O
158	GND
159	SYS_DATA_L[27]	I/O
160	SYS_DATA_L[25]	I/O
161	SYS_DATA_L[23]	I/O
162	3.3v
163	SYS_DATA_L[21]	I/O
164	GND
165	SYS_DATA_L[19]	I/O
166	SYS_DATA_L[17]	I/O
167	SYS_DATA_L[15]	I/O
168	SYS_DATA_L[13]	I/O
169	3.3v
170	3.3v
171	GND
172	SYS_DATA_L[10]	I/O
173	SYS_DATA_L[8]	I/O
174	SYS_DATA_L[6]	I/O
175	3.3v
176	SYS_DATA_L[5]	I/O
177	GND
178	SYS_DATA_L[2]	I/O
179	SYS_DP7	I/O
180	SYS_DP6	I/O
181	SYS_DP4	I/O
182	3.3v
183	SYS_DP3	I/O
184	SYS_DP1	I/O
185	SYS_ADDR[31]	I/O
186	SYS_ADDR[30]	I/O
187	GND
188	BUS_CLK0	Unused
PIN#	SIGNAL NAME	TYPE
189	GND
190	SYS_ADDR[27]	I/O
191	3.3v
192	SYS_ADDR[24]	I/O
193	SYS_ADDR[22]	I/O
194	GND
195	BUS_CLK1	I
196	GND
197	3.3v
198	SYS_ADDR[20]	I/O
199	SYS_ADDR[18]	I/O
200	SYS_ADDR[16]	I/O
201	SYS_ADDR[15]	I/O
202	SYS_ADDR[14]	I/O
203	GND
204	3.3v
205	SYS_ADDR[10]	I/O
206	SYS_ADDR[8]	I/O
207	SYS_ADDR[6]	I/O
208	SYS_ADDR[4]	I/O
209	GND
210	SYS_ADDR[2]	I/O
211	SYS_ADDR[1]	I/O
212	GND
213	3.3v
214	SYS_ADDR_BUS_GR#	I
215	SYS_GBL#	I/O
216	SYS_TSIZ[0]	I/O
217	3.3v
218	GND
219	SYS_TSIZ[2]	I/O
220	SYS_TSIZ[1]	I/O
221	SYS_TS#	I/O
222	SYS_TT[3]	I/O
223	TMS	I
224	GND
225	+5v
226	SYS_TT[0]	I/O
227	CHECKSTOP#	I/O
228	SYS_TT[4]	I/O
229	SYS_CI#	I/O
230	GND
231	SYS_ADDR_BUS_RQ#	O
232	SYS_TBRST#	I/O
PIN#	SIGNAL NAME	TYPE
233	DPE#	I
234	TDO	O
235	HRESET_A#	I
236	Reserved	Unused
237	GND
238	+5v
239	SMI#	I
240	INT_A#	I
241	L2_PD0	Unused
242	GND
243	MCP_A#	I
244	L2_PD1	Unused
PIN#	SIGNAL NAME	TYPE
245	+5v
246	GND
247	TBEN	I/O
248	SYS_ADDRP[2]	I/O
249	SYS_ADDRP[3]	I/O
250	L2_FLUSH#	Unused
251	L2_BG#	Unused
252	L2_INH#	Unused
253	L2_DISABLE#	Unused
254	FREQ_ID1	I
255	GND
256	FREQ_ID3	I

Pin No.	Signal Name
1	SYS_BR#
2	TC2
3	TC1
4	TC0
5	BG#
6	nc
7	RSRV#
Pin No.	Signal Name
8	SRESET_A#
9	nc
10	HRESET_A#
11	INT_A#
12	DPE#
13	APE#
14	GND

Section 1 CPU Card