Section 1
DRAM and ROM
This Section discusses the DRAM and ROM subsystems of the reference design. The
DRAM and ROM controllers are located inside the 660 Bridge. The DRAM modules are
plug into cards (SIMMs). The ROM is a Flasht device which is socketed on the
motherboard.
The reference design system memory is composed of DRAM modules. The 660 Bridge
memory controller interfaces the system memory to the rest of the reference design. The
memory controller (MC) handles CPU and PCI access to memory, DRAM refreshing, and
DRAM error checking.
The actual operation of the MC is covered in detail in the 660 Bridge User's Manual. The
purpose of this section is to describe how the MC capabilities are implemented on the
reference design.
The reference design supports up to 256M of DRAM, arranged as eight banks of the
following:
- Industry standard 70ns, 72-pin, 4-byte SIMM
- One parity bit per byte, which can be used for parity or ECC
- Presence detect bits
- Asynchronous DRAM, page mode, or EDO (hyper-page mode).
Table 1 shows some supported devices. Different banks may use different sized SIMMs.
Both of the SIMMs in the same bank must be the same size.
| Table 1. Supported DRAM Modules
|
| Size
|
Organization
|
IBM Part Number
|
DRAM Data Sheet
|
| 4MB
|
1M x 36b
|
IBM11E1360BA
|
MMDS14DSU-00
|
| 8MB
|
2M x 36b
|
IBM11E2360BA
|
MMDS22DSU-00
|
| 16MB
|
4M x 36b
|
IBM11E4360B
|
MMDS26DSU-00
|
| 32MB
|
8M x 36b
|
IBM11E8360B
|
MMDS27DSU-00
|
1.1.1 Memory Controller (DRAM)
The 660 Bridge contains a high performance memory controller which is extensively
programmable. Refer to the 660 Bridge User's Manual for details.
In general, the MC is configured by the reference firmware for 70ns, page mode,
asynchronous, parity DRAM arranged as pairs of 4-byte, 72-pin modules (see the
Registers and System Setup section for more setup information). EDO timings are not
used, ECC memory checking is disabled, and parity checking is enabled. These settings
can be modified as desired by the firmware.
1.1.2 Organization
The 4-byte (plus 4 parity bit) wide DRAM modules (SIMMs) are arranged in pairs to form
8-byte (plus 8 parity bit) wide memory banks, as shown in Figure 1 and Figure 2. The 2
SIMMs in each bank must be the same size.
Combining the internal organization of the SIMMs (found in the respective data sheets) with
the bank organization (found in Figure 1 and Figure 2) shows that each parity bit is
accessed with the associated data byte. The 660 bridge uses this standard DRAM module
organization for both parity and ECC modes of operation.
1.1.3 Refresh
The memory controller in the 660 bridge provides a flexible refresh capability for the
reference design. See The 660 Bridge User's Manual for more information.
The ISA bus bridge provides the ISA_REFRESH# signal to refresh ISA bus memory. Refer
to the SIO data book for more information.
1.1.4 DRAM Presence Detection
Figure 1 and Figure 2 show the arrangement of the presence detect bits, MPD[31:0], which
the firmware uses to detect and identify installed DRAM modules. See the CPU Slot Signal
Descriptions in the CPU Bus section.
1.1.5 DRAM Bank Rules
All the DRAM SIMMs must:
- Be asynchronous, 72-pin, 4-byte SIMMs with presence detect bits.
- Be capable of operating at the timings selected by the memory controller registers.
- Be page mode if page mode operation is selected. If EDO operation is selected, then
all SIMMs must be EDO.
- Be capable of the selected type of memory data checking (none or parity). ECC
mode uses standard parity DRAM SIMMs.
Additionally, each SIMM in a given pair must be the same size and addressing (row vs.
column) type.
The reference design uses an AMD AM29F040-120 Flasht ROM to contain the POST and
boot code. It is recommended that vital product data such as the motherboard speed and
native I/O complement be programmed into in this device. It is possible to program the
Flash before or during the manufacturing process. For more information, see The 660
Bridge User's Manual and CPU to ROM Transfers in the CPU Bus section of this document.
See the System Firmware section for information on the system firmware, and the
Registers and System Setup section for system setup information.
1.2.1 PCI Bus ROM
The reference design uses the direct-attach or PCI ROM attachment method. The ROM
is connected to the PCI_AD[31:0] lines in a manner that makes it invisible to the PCI agents.
The reference design uses 75W series isolation resistors to decouple the ROM from the
PCI bus.
1.2.2 Remote ROM
The reference design has pads on the motherboard for a remote-attach ROM, which is
located on the X-bus and accessed through the ISA bridge. The (SIO) ISA bridge currently
installed on the reference design does not support this function, so it is not implemented.
1.2.3 ROM Read, Write, and Write Protect
The ROM used on the reference design is an AMDt Flasht ROM, 29F040. This device
is read like a standard ROM. It can also be written to using a special protocol. The ROM
can be placed in write-protected mode by writing to the 660 Bridge BCR. For more
information, see The 660 Bridge User's Manual and CPU to ROM Transfers in the CPU Bus
section of this document.