Section 1
Clocks

The 604 SMP Reference Design provides a separate CPU clock line for each CPU bus agent or other CPU clock consumer. The CPU bus clocks used on the reference design motherboard are generated by the master PLL, which supplies all of the motherboard CPU clocks. It also supplies three CPU clocks to each CPU slot. When required, additional CPU bus clocks can be generated on a CPU card using another PLL.

The reference design also provides a separate PCI clock for each PCI agent. These clocks are generated by the PCI PLL on the motherboard, which is synchronized to the master PLL. The PLL produces PCI clocks that are nominally not delayed from the CPU clock.

Other clocks in the system are generated by oscillators or crystals which are provided on the motherboard, and are located close to the intended load.

1.1 CPU Clocks

As shown in Figure 1, the master PLL is a Motorolat MPC970 PLL clock generator. The master PLL is configured to drive all of its outputs at the same frequency (even the PCI_CLK outputs). The master PLL supplies:

BCLK3, BCLK4, and 2X_PCLK CPU Slot 1
BCLK1, BCLK2, and PCLK_EN CPU Slot 2
BCLK0 and BCLK_EN 660 Bridge
PCI_CLK[5:1] L2 TagRAM and SRAM clocks
PCI_CLK[0] Seed clock for PCI clock PLL
PCI_CLK[6] Spare

1.1.1 CPU Card Clock Repeater

The reference design motherboard supplies three CPU clocks to each CPU slot. If a CPU card requires more than 2 clocks, a 'zero delay' clock repeater such as the Motorolat MPC930 PLL can be used on the CPU card to generate the additional clocks, using one of the supplied CPU clocks as the seed clock.

1.1.2 CPU Clock Physical Design Rules

The reference design board was physically designed with careful attention to the fact that, at PowerPC operating frequencies, the circuit board itself becomes a component that materially affects circuit behavior. The following steps were used to control this:

Noise generation, reflections, and impedance mismatches were reduced by routing the CPU clock lines on internal planes of the motherboard with (frequently grounded) ground traces running in adjacent wiring channels.
The number of vias per clock line was minimized.
Source termination resistors were chosen according to the MPC970 data sheet recommendations.
EMC capacitors were added to the clock nets.

To minimize clock skew, each of the CPU clock lines was made the same total length. In the case of the clock lines that run to CPU cards, part of the clock length appears on the motherboard, and part of it appears on the CPU card. Each of the clock lines runs only from the master PLL driver to the clock receiver of the CPU clock consumer. Also see the Physical Design section for more information.

1.2 CPU Clock Control Logic

The reference design automatically sets the CPU bus clock frequency and the configuration bits of the PLLs in the 604 CPU cards. As shown in Figure 2, the clock control logic makes these decisions based on the value of the presence detect bits from each CPU slot and the state of J17. The reference design:

Supplies the same frequency CPU clocks to each CPU slot.
Supplies the same PLL configuration information to each CPU slot.
Selects the fastest allowed bus clock frequency and CPU frequency that is acceptable to both CPUs.

The clock control logic is implemented in the frequency select PAL (FRQSEL) and an 'F157 quad 2:1 Multiplexer.

1.2.1 Clock Logic Input - J17

Regardless of the values present on the CPU slot PD bits, if J17 is installed, the clock control logic sets the CPU clock speed to 60MHz, and will set the CPU PLL control bits to 0001 (1:1 CPU to bus clock ratio and a 4:1 PLL to CPU clock ratio).

1.2.1.1 Clock Logic Input - CPU Slot PD Bits

As shown in Figure 2, the clock control logic receives the speed capability information from each CPU slot on the presence detect bits for that slot. The encoding of these bits is shown in Table 1.

Table 1. CPU Slot PD Bit Encoding

CPU_PD[0:3]

CPU Type

0000

No CPU on card.

0001

100 MHz CPU

0010

120 MHz CPU

0011

132 MHz CPU

0100

150 MHz CPU

0101

167 MHz CPU

0110

180 Mhz CPU

0111-1110

Reserved

1111

No CPU card present.

1.2.1.2 Clock Logic Output - CPU Bus Clock Frequency Select

The clock control logic controls the frequency of the CPU bus clocks by setting the master PLL (MPC970) REFSEL input to select either 60MHz or 66MHz operation. This instructs the MPC970 to select either the crystal or the oscillator as the source of the seed frequency.

1.2.1.3 Clock Logic Output - 604 PLL Configuration

The clock control logic asserts CPU_FREQ_CFG[0:3] to both CPU cards, which connect these lines to the PLL_CFG[0:3] inputs of the 604 CPU. This information causes the 604 to configure its onboard PLL as described in the 604 User's Manual. This configuration determines the ratio between the 604 internal CPU clock, the 604 internal PLL frequency, and the CPU bus clock.

1.2.1.4 Clock Logic Transfer Function

Table 2 shows the outputs of the clock control logic as a function of the inputs. The headings along the top of the table show the presence detect bits from CPU slot 1, along with their meanings. The headings on the left side of the table show the same information for CPU slot 2.

Except as noted, each of the entries in the body of the table shows the CPU bus clock as either 60 or 66 MHz, and also shows the value that the logic asserts on the CPU_FREQ_CFG[0:3] lines to both CPU cards.

Table 2. CPU Clock Control Logic

Frequency Table
Bus Speed (Mhz)
and
PLL Settings
(freq_id 0,1,2,3)

CPU Card Slot 1 PD[0:3]

0000

0001

0010

0011

0100

0101

0110

0111

1000- 1110

1111

No CPU

100 Mhz CPU

120 Mhz CPU

132 Mhz CPU

150 Mhz CPU

167 Mhz CPU

180 Mhz CPU

Rsrvd

Rsrvd

No card pres.

CPU Card Slot 2 PD
[0:3]

0000

No CPU

ERR

66
(1100)

60
(0100)

66
(0100)

60
(0110)

66
(0110)

60
(1000)

ERR

ERR

ERR

0001

100 Mhz CPU

66
(1100)

66
(1100)

66
(1100)

66
(1100)

66
(1100)

66
(1100)

66
(1100)

66
(1100)
**

60
(0001)

66
(1100)

0010

120 Mhz CPU

60
(0100)

66
(1100)

60
(0100)

60
(0100)

60
(0100)

60
(0100)

60
(0100)

60
(0100)
**

60
(0001)

60
(0100)

0011

132 Mhz CPU

66
(0100)

66
(1100)

60
(0100)

66
(0100)

66
(0100)

66
(0100)

66
(0100)

66
(0100)
**

60
(0001)

66
(0100)

0100

150 Mhz CPU

60
(0110)

66
(1100)

60
(0100)

66
(0100)

60
(0110)

60
(0110)

60
(0110)

60
(0110)
**

60
(0001)

60
(0110)

0101

167 Mhz CPU

66
(0110)

66
(1100)

60
(0100)

66
(0100)

60
(0110)

66
(0110)

66
(0110)

66
(0110)
**

60
(0001)

66
(0110)

0110

180 Mhz CPU

60
(1000)

66
(1100)

60
(0100)

66
(0100)

60
(0110)

66
(0110)

60
(1000)

60
(1000)
**

60
(0001)

60
(1000)

0111

Rsrvd

ERR

66
(1100)
**

60
(0100)
**

66
(0100)
**

60
(0110)
**

66
(0110)
**

60
(1000)
**

ERR

ERR

ERR

1000- 1110

Rsrvd

ERR

60
(0001)

60
(0001)

60
(0001)

60
(0001)

60
(0001)

60
(0001)

ERR

ERR

ERR

1111

No card pres.

ERR

66
(1100)

60
(0100)

66
(0100)

60
(0110)

66
(0110)

60
(1000)

ERR

ERR

ERR

Indicates a non-optimized system configuration. One of the two CPU slots is populated with a faster CPU card than is in the other slot. The clock control logic will operate both CPUs at the slower of the two CPU clock speeds. One CPU will not be operating at full rated speed.

Indicates an unsupported configuration on one of the slots. The clock control logic will set the bus clock frequency to 60 Mhz and configure the CPU internal clock for 1:1 mode (PLL @ 4x). Software should disable the slot that is reporting the reserved PD bit value (see Processor En able Register, Port 0871h).

ERR

Indicates an error condition. The clock control logic sets the CPU bus clock frequency to 60MHz and configure the CPU internal clocks for 1:1 mode.

**

Indicates that one of the CPU cards is using reserved PD[0:3] pattern 0111. The clock control logic sets the bus clock frequency and CPU_FREQ_CFG[0:3] lines as shown. Developers may wish to use this PD code for experimental devices.

1.2.2 Frequency Select PAL Equations


TITLE    Zapatos Frequency Selection Logic
PATTERN  Frqsel1.PDS
REVISION 0
COMPANY  ibm
DATE     09/20/95

CHIP   frqsel1  PAL20L8

;------------------------- PIN Declarations ---------  28plcc PIN
;PIN             NC                               ;             1
PIN  1           PID0_0                           ; INPUT       2
PIN  2           PID0_1                           ; INPUT       3
PIN  3           PID0_2                           ; INPUT       4
PIN  4           PID0_3                           ; INPUT       5
PIN  5           PID1_0                           ; INPUT       6
PIN  6           PID1_1                           ; INPUT       7
;PIN             NC                               ; INPUT       8
PIN  7           PID1_2                           ; INPUT       9
PIN  8           PID1_3                           ; INPUT       10
PIN  9           ID0                              ; INPUT       11
PIN  10          ID1                              ; INPUT       12
PIN  11          ID2                              ; INPUT       13
;PIN  12         GND                              ;             14
;PIN             NC                               ;             15
PIN  13          SPARE0                           ; INPUT       16
PIN  14          ID3                              ; INPUT       17
PIN  15          FRQID0           COMBINATORIAL   ; OUTPUT      18
PIN  16          FRQID1           COMBINATORIAL   ; OUTPUT      19
PIN  17          FRQID2           COMBINATORIAL   ; OUTPUT      20
PIN  18          SEL0             COMBINATORIAL   ; OUTPUT      21
;PIN             NC                               ;             22
PIN  19          SEL0_NA          COMBINATORIAL   ; OUTPUT      23
PIN  20          SEL0_NB          COMBINATORIAL   ; OUTPUT      24
PIN  21          FASTBUS_         COMBINATORIAL   ; OUTPUT      25
PIN  22          FRQID3           COMBINATORIAL   ; OUTPUT      26
PIN  23          FRQOVR_                          ; INPUT       27
;PIN 24          VCC                              ;             28

;------------------------------- Boolean Equation Segment ------

FRQID0.TRST = VCC
FRQID1.TRST = VCC
FRQID2.TRST = VCC
FRQID3.TRST = VCC
FASTBUS_.TRST=VCC
SEL0.TRST = VCC
SEL0_NA.trst = VCC
SEL0_NB.trst = VCC

/FASTBUS_  =  /ID0* /ID2* ID3* FRQOVR_
             +/ID0* /ID1* ID3* FRQOVR_

/FRQID0    =   ID0
            + /ID2* /ID3
            +  ID2*  ID3
            + /ID0*  ID1* /ID2*  ID3
            + /FRQOVR_

/FRQID1    =   ID0
            + /ID0*  ID1*  ID2
            + /ID0* /ID1* /ID2* /ID3
            + /FRQOVR_

/FRQID2    =   ID0
            +  ID2
            + /ID0* /ID1
            + /FRQOVR_

/FRQID3    =  /ID0* ID1* ID2* FRQOVR_
            + /ID0*/ID2* ID3* FRQOVR_
            + /ID0*/ID1* ID2* FRQOVR_
            + /ID0* ID2*/ID3* FRQOVR_

/SEL0    =                         /PID0_3*/PID1_0*/PID1_1*/PID1_2* PID1_3
         + /PID0_0* PID0_1*                /PID1_0*/PID1_1
         + /PID0_0* PID0_1*/PID0_2*        /PID1_0* PID1_1* PID1_2
         + /PID0_0*/PID0_1*         PID0_3*/PID1_0*/PID1_1*/PID1_2* PID1_3
         + /PID0_0*/PID0_1* PID0_2* PID0_3*/PID1_0*/PID1_1*/PID1_2* PID1_3
         + /SEL0_NA
         + /SEL0_NB

/SEL0_NA = /PID0_0*/PID0_1*/PID0_2*/PID0_3*/PID1_0*/PID1_1*         PID1_3
         + /PID0_0*/PID0_1*/PID0_2*/PID0_3*/PID1_0*         PID1_2*/PID1_3
         + /PID0_0*/PID0_1*/PID0_2*/PID0_3*/PID1_0* PID1_1*/PID1_2
         + /PID0_0* PID0_1* PID0_2* PID0_3*/PID1_0* PID1_1* PID1_2*/PID1_3
         + /PID0_0*/PID0_1* PID0_2* PID0_3*/PID1_0*/PID1_1* PID1_2*/PID1_3
         + /PID0_0* PID0_1* PID0_2*        /PID1_0* PID1_1*/PID1_2
         + /PID0_0* PID0_1*/PID0_2* PID0_3*/PID1_0* PID1_1*/PID1_2*/PID1_3

/SEL0_NB  = PID0_0* PID0_1* PID0_2* PID0_3*/PID1_0*/PID1_1*         PID1_3
          + PID0_0* PID0_1* PID0_2* PID0_3*/PID1_0*         PID1_2*/PID1_3
          + PID0_0* PID0_1* PID0_2* PID0_3*/PID1_0* PID1_1*/PID1_2

1.2.3 Clock Freezing

Some of the CPU clocks generated by the master PLL may not be required. For example, if no L2 is installed in the system, then the PCI_CLK[5:1] outputs of the MPC970 will not be required. The ability to stop (freeze) the unused clocks is useful to reduce run-time power consumption and EMI emissions.

The MPC970 can freeze any set of output clocks in the low state, while allowing the other clocks to continue running. The freeze command is given to the MPC970 via a two wire synchronous serial interface that originates in the system EPLD. See the clock freeze register description in the System EPLD section for more information on activating this feature.

Firmware can read the presence detect bits of the L2 and CPU card slots to determine which slots have devices present. For card slots which are not populated, firmware can disable the BUS_CLKs for those slot.

This function can also be used by power management functions to further reduce power consumption of the motherboard by freezing the clocks of devices which have been placed in a power managed mode.

1.3 PCI Clocks

The PCI clocks are generated by an AMCCt 4403B PLL zero-delay clock generator, which divides the CPU clock by two and synchronizes the output clocks to the CPU seed clock. Five of the PCI clocks are used on the motherboard, and one PCI_CLK is provided for each of the two PCI expansion slots.

To minimize PCI to PCI clock skew, the PCI clock lengths have been made as equal as was feasible. Physical design of these traces follows the same rules as were used for the CPU clock traces. Also see the Physical Design section for more information.

1.3.1 PCI Bus speed Selection

The CPU:PCI bus clock ratio can be set to either 2:1 or 1:1.

To make the CPU:PCI ratio 2:1, install a jumper between pin 2 and pin 3 of J30.
To make the CPU:PCI ratio 1:1, install a jumper between pin 1 and pin 2 of J30.
This mode has not been tested and is not recommended.

1.4 ISA Bus Clock

The ISA bridge derives the ISA SYSCLK from the PCI clock by dividing it by 4 or 3. This is controlled by the ISA Clock Divisor Register within the SIO chip. For PCI bus speeds of 33 and 30 Mhz, a divide by 4 should be selected to give ISA clock frequencies of 8.25 MHz and 7.5 MHz respectively.

1.5 Oscillators, Crystals, and Clocks

Table 3 shows the various sources of frequency generation in the system.

Table 3. Supported DRAM Modules

Clock

Source

Frequency

Reference crystal to MPC970 (60 Mhz CPU bus clock reference )

Y13 or Y8 crystal

15 MHz

Reference clock to MPC970 (66MHz CPU bus clock reference )

M10 oscillator

16.5 MHz

SCSI Clock reference for NCR53C810

Y1 oscillator

40 MHz

Ethernet clock reference for AM79C970

Y19 crystal

20 MHz

ISA OSC clk and 8254 timer reference for the ISA bridge

Y6 oscillator

14.3181 MHz

PC87332 SuperI/O baud rate reference for serial ports

Y9 oscillator

24 MHz

Reference crystal for Business audio subsystem CS4232 controller

Y2 crystal

24.576 MHz

Reference crystal for Business audio subsystem CS4232 controller

Y12 crystal

16.934 MHz

Reference crystal for Business audio subsystem YMF289S

Y11 or Y15 crystal

33.8688 MHz

Reference clock for bus clock shutdown interface. EPLD, MPC970

Y7 oscillator

1.8432 MHz

Reference crystal for power management controller

Y4 crystal

16 MHz

Reference crystal for RTC circuit DS1385

Y3 crystal

32.768 kHz

Reference crystal for Keyboard/Mouse controller

Y5 crystal

12 MHz

Table 1. CPU Slot PD Bit Encoding
CPU_PD[0:3]	CPU Type
0000	No CPU on card.
0001	100 MHz CPU
0010	120 MHz CPU
0011	132 MHz CPU
0100	150 MHz CPU
0101	167 MHz CPU
0110	180 Mhz CPU
0111-1110	Reserved
1111	No CPU card present.

Table 2. CPU Clock Control Logic
Frequency Table Bus Speed (Mhz) and PLL Settings (freq_id 0,1,2,3)			CPU Card Slot 1 PD[0:3]
			0000	0001	0010	0011	0100	0101	0110	0111	1000- 1110	1111
			No CPU	100 Mhz CPU	120 Mhz CPU	132 Mhz CPU	150 Mhz CPU	167 Mhz CPU	180 Mhz CPU	Rsrvd	Rsrvd	No card pres.
CPU Card Slot 2 PD [0:3]	0000	No CPU	ERR	66 (1100)	60 (0100)	66 (0100)	60 (0110)	66 (0110)	60 (1000)	ERR	ERR	ERR
	0001	100 Mhz CPU	66 (1100)	66 (1100)	66 (1100)	66 (1100)	66 (1100)	66 (1100)	66 (1100)	66 (1100) **	60 (0001)	66 (1100)
	0010	120 Mhz CPU	60 (0100)	66 (1100)	60 (0100)	60 (0100)	60 (0100)	60 (0100)	60 (0100)	60 (0100) **	60 (0001)	60 (0100)
	0011	132 Mhz CPU	66 (0100)	66 (1100)	60 (0100)	66 (0100)	66 (0100)	66 (0100)	66 (0100)	66 (0100) **	60 (0001)	66 (0100)
	0100	150 Mhz CPU	60 (0110)	66 (1100)	60 (0100)	66 (0100)	60 (0110)	60 (0110)	60 (0110)	60 (0110) **	60 (0001)	60 (0110)
	0101	167 Mhz CPU	66 (0110)	66 (1100)	60 (0100)	66 (0100)	60 (0110)	66 (0110)	66 (0110)	66 (0110) **	60 (0001)	66 (0110)
	0110	180 Mhz CPU	60 (1000)	66 (1100)	60 (0100)	66 (0100)	60 (0110)	66 (0110)	60 (1000)	60 (1000) **	60 (0001)	60 (1000)
	0111	Rsrvd	ERR	66 (1100) **	60 (0100) **	66 (0100) **	60 (0110) **	66 (0110) **	60 (1000) **	ERR	ERR	ERR
	1000- 1110	Rsrvd	ERR	60 (0001)	60 (0001)	60 (0001)	60 (0001)	60 (0001)	60 (0001)	ERR	ERR	ERR
	1111	No card pres.	ERR	66 (1100)	60 (0100)	66 (0100)	60 (0110)	66 (0110)	60 (1000)	ERR	ERR	ERR
	Indicates a non-optimized system configuration. One of the two CPU slots is populated with a faster CPU card than is in the other slot. The clock control logic will operate both CPUs at the slower of the two CPU clock speeds. One CPU will not be operating at full rated speed.
	Indicates an unsupported configuration on one of the slots. The clock control logic will set the bus clock frequency to 60 Mhz and configure the CPU internal clock for 1:1 mode (PLL @ 4x). Software should disable the slot that is reporting the reserved PD bit value (see Processor En able Register, Port 0871h).
ERR	Indicates an error condition. The clock control logic sets the CPU bus clock frequency to 60MHz and configure the CPU internal clocks for 1:1 mode.
**	Indicates that one of the CPU cards is using reserved PD[0:3] pattern 0111. The clock control logic sets the bus clock frequency and CPU_FREQ_CFG[0:3] lines as shown. Developers may wish to use this PD code for experimental devices.

Table 3. Supported DRAM Modules
Clock	Source	Frequency
Reference crystal to MPC970 (60 Mhz CPU bus clock reference )	Y13 or Y8 crystal	15 MHz
Reference clock to MPC970 (66MHz CPU bus clock reference )	M10 oscillator	16.5 MHz
SCSI Clock reference for NCR53C810	Y1 oscillator	40 MHz
Ethernet clock reference for AM79C970	Y19 crystal	20 MHz
ISA OSC clk and 8254 timer reference for the ISA bridge	Y6 oscillator	14.3181 MHz
PC87332 SuperI/O baud rate reference for serial ports	Y9 oscillator	24 MHz
Reference crystal for Business audio subsystem CS4232 controller	Y2 crystal	24.576 MHz
Reference crystal for Business audio subsystem CS4232 controller	Y12 crystal	16.934 MHz
Reference crystal for Business audio subsystem YMF289S	Y11 or Y15 crystal	33.8688 MHz
Reference clock for bus clock shutdown interface. EPLD, MPC970	Y7 oscillator	1.8432 MHz
Reference crystal for power management controller	Y4 crystal	16 MHz
Reference crystal for RTC circuit DS1385	Y3 crystal	32.768 kHz
Reference crystal for Keyboard/Mouse controller	Y5 crystal	12 MHz

Section 1 Clocks