Section 1
PCI Bus

The reference design provides two 5.0v or 3.3v, 33MHz, 32 bit, PCI expansion slots via the riser card (see the Riser section for riser card information). The PCI bus implementation on the reference design is provided by the 660 Bridge, and it features:

S PCI I/O reads and writes.

S PCI memory reads and writes.

S PCI configuration reads and writes.

S PCI interrupt acknowledge reads.

The SCSI controller, the Ethernet controller, the Multi-Processor Interrupt Controller (MPIC), and the ISA bridge also reside on the PCI bus.

PCI Transaction Decoding and PCI Transaction Details in the PCI Bus section discuss the response of the reference design to transactions initiated by a PCI busmaster. See the CPU Bus section for information on accessing the PCI bus from the CPU.

Succeeding sections discuss PCI bus arbitration, configuration transaction, and other PCI topics.

For information on PCI interrupts and MPIC, see the Exceptions section. Also see the MPIC data sheet.

For information the Ethernet and SCSI controllers, see the I/O Subsystems section. Also see the controller data sheets.

For more information on the ISA bridge, see the ISA and X-Bus section. Also see the ISA bridge data sheet.

1.1 PCI Transaction Decoding

When a PCI bus master initiates a transaction on the PCI bus, the transaction either misses and is master aborted, or it is claimed by a PCI target. The target can be either the 660 Bridge or another PCI target.

1.1.1 PCI Transaction Decoding By Bus Command

Table 1 shows the responses of the 660 Bridge and other agents to various PCI bus transactions initiated by a PCI bus master other than the 660 Bridge. As shown in Table 1, the 660 Bridge ignores (No response) all PCI bus transactions except PCI memory read and write transactions, which it decodes as possible system memory accesses.

Table 1. Reference Design Responses to PCI_C[3:0] Bus Commands

C 3:0

PCI Bus Command

Can a PCI Bus
Master-Initiate this Transaction?

660 Bridge
Response to the Transaction

Can Another PCI Target Claim the Transaction?

0000

Interrupt Acknowledge

No. Only the 660 Bridge is allowed to initiate.

None

Yes. The ISA bridge is intended to be the target.

0001

Special Cycle

Yes

None

Yes

0010

I/O Read

Yes

None

Yes

0011

I/O Write

Yes

None

Yes

0100

Reserved

No. Reserved

None

n/a

0101

Reserved

No. Reserved

None

n/a

0110

Memory Read

Yes

System memory read

Yes, if no address conflict.

0111

Memory Write

Yes

System memory write

Yes, if no address conflict.

1000

Reserved

No. Reserved

None

n/a

1001

Reserved

No. Reserved

None

n/a

1010

Configuration Read

No. Only 660 Bridge.

None

Yes

1011

Configuration Write

No. Only 660 Bridge.

None

Yes

1100

Memory Read Multiple

Yes

System memory read

Yes, if no address conflict.

1101

Dual Address Cycle

Yes

None

Yes

1110

Memory Read Line

Yes

System memory read

Yes, if no address conflict.

1111

Memory Write and Invalidate

Yes

System memory write

Yes, if no address conflict.

1.1.2 PCI Memory Transaction Decoding By Address Range

When a PCI bus master transaction is decoded by bus command as a system memory read or write, the 660 Bridge checks the address range. Table 2 shows the mapping of PCI bus master memory accesses to system memory. This is the mapping that the 660 Bridge uses when it decodes the bus command to indicate a system memory access.

Unless the IGN_PCI_AD31# signal is asserted, PCI memory accesses in the 0 to 2G address range are ignored by the 660 Bridge. There is no system memory access, no snoop cycle, and the 660 Bridge does not claim the transaction. When the IGN_PCI_AD31# signal is asserted, the 660 Bridge maps PCI memory accesses from 0 to 2G directly to system memory at 0 to 2G. PCI memory accesses from 2G to 4G are mapped to system memory from 0 to 2G.

Table 2. Mapping of PCI Memory Space, Part 1

PCI Bus
Address

Other Conditions

Target Cycle
Decoded

Target
Address

Notes

0 to 2G

IGN_PCI_AD31#
Deasserted

Not Decoded

N/A

No Response.

IGN_PCI_AD31#
Asserted

System Memory *

0 to 2G

Snooped by caches.

2G to 4G

System Memory *

0 to 2G

Snooped by caches.

Note:
*Memory does not occupy this entire address space. Accesses to unoccupied space are not decoded.

PCI memory accesses that are mapped to system memory cause the 660 Bridge to claim the transaction, access system memory, arbitrate for the CPU bus, and broadcast a snoop operation on the CPU bus. A detailed description of the snoop process is presented in the 660 Bridge User's Manual.

Table 3 gives a more detailed breakdown of the reference design response to PCI memory transactions in the 0 to 2G range. Note that the preferred mapping of PCI memory is from 16M to 1G-2M so that it can be accessed by both the CPU and by PCI bus masters.

Table 3. Mapping of PCI Memory Space, Part 2

PCI Bus Address

Target Resource

System Memory Address

Snoop Address

2G to 4G

System memory (1)

0 to 2G

0 to 2G

1G-2M to 2G

Reserved (2)

No system memory access. The 660 Bridge ignores PCI memory transactions in this range.

No snoop.

16M to 1G-2M

PCI Memory

0 to 16M

PCI/ISA Memory (3)

Notes:

1) The 660 Bridge maps PCI bus master memory transactions in the 2G to 4G range to system memory, and the CPU is unable to initiate PCI memory transactions to this address range, so do not map devices to this PCI memory address range.

2) The CPU (through the 660 Bridge) can not access the 1G-2M to 2G address range, so do not map PCI devices herein unless the CPU will not access them.

3) Transactions initiated on the PCI bus by the ISA bridge on behalf of an ISA bus master only (IGN_PCI_AD31# asserted for an SIO), are forwarded to system memory and broadcast snooped to the CPU bus from 0 to 16M. If this is not an ISA bus master transaction, then the 660 Bridge ignores it. Note that the 660 Bridge will also forward PCI transactions from 16M to 2G if IGN_PCI_AD31# is asserted during an ISA-bridge-mastered transaction, and that this capability is not normally used.

1.1.3 PCI I/O Transaction Decoding

The 660 Bridge initiates PCI I/O transactions on behalf of the CPU. Other PCI bus masters are also allowed to initiate PCI I/O transactions. Table 4 shows the reference design mapping of PCI I/O transactions. The 660 Bridge ignores PCI I/O transactions.

PCI/ISA I/O is mapped to PCI I/O space from 0 to 64K. The ISA bridge subtractively decodes these transactions (and PCI memory transactions from 0 to 16M). Other devices may actively decode and claim these transactions without contention.

PCI I/O is assigned from 16M to 1G-8M.

Table 4. Mapping of PCI Master I/O Transactions

PCI Bus Address

Target Resource

Other System Activity

1G-8M to 4G

Reserved (1)

The 660 Bridge ignores I/O transactions initiated by PCI bus masters.

16M to 1G-8M

PCI I/O devices

8M to 16M

Reserved (1)

64K to 8M

Reserved (2)

0 to 64K

PCI/ISA I/O

Notes:

1) The CPU (through the 660 Bridge) can not access this address range, so do not map PCI devices herein unless the CPU will not access them.

2) In contiguous mode, the CPU (through the 660 Bridge) can create PCI I/O addresses in the 64K to 8M range. In non-contiguous mode, the CPU can only access PCI addresses from 0 to 64K.

1.1.4 ISA Master Considerations

Since the reference design implements IGN_PCI_AD31# and uses an Intel SIO, memory transactions produced on the PCI bus by the ISA bridge on behalf of an ISA master are forwarded to system memory at the corresponding address (0 -16M).

If ISA masters are utilized and the SIO is programmed to forward their cycles to the PCI bus, then no other PCI device (e.g., video) is allowed to be mapped at the same addresses because contention would result.

The SIO chip contains registers to control which ranges of ISA addresses are forwarded to the PCI bus.

ISA masters cannot access any PCI memory.

For more information on the handling of ISA bus master operations, see the 660 Bridge User's Manual and the SIO data book.

1.2 PCI Transaction Details

Details of the reference design implementation of various PCI transactions, including sequencing, timing, and interactions with the CPU bus, are found in the 660 Bridge User's Manual.

PCI bus masters are not able to access the boot ROM, the BCRs in the 660 Bridge, or the CPU bus.

1.2.1 Bus Snooping on PCI to Memory Cycles

Each time a PCI (or ISA) bus master accesses memory, (and once again for each time a PCI burst crosses a cache block boundary) the 660 Bridge broadcasts a snoop operation on the CPU bus. If the CPU signals an L1 snoop hit by asserting ARTRY#, the 660 Bridge retries the PCI transaction. The ISA bridge then removes the grant from the PCI agent, who (according to PCI protocol) releases the bus for at least one cycle and then arbitrates again. Meanwhile, the 660 Bridge grants the CPU bus to the CPU, allowing it to do a snoop push. Then the PCI agent again initiates the original transaction.

During the transaction, the 660 Bridge L2 cache is monitoring the memory addresses. The L2 takes no action on L2 misses and read hits. If there is an L2 write hit, the L2 marks that block as invalid, does not update the block in SRAM, and does not affect the PCI transaction. L2 operations have no effect on PCI to memory bursts.

1.2.2 PCI Peer to PCI Peer Transactions

Peer to peer PCI transactions are supported consistently with the memory maps of Table 1, Table 2, Table 3, and Table 4, which, together, show the range of different bus command transactions that are supported. The SIO can not perform PCI memory transactions to a PCI peer because all SIO memory transactions are mapped to system memory.

1.2.3 PCI to System Memory Transactions

PCI to system memory transactions are described in detail in the 660 Bridge User's Manual.

Single and burst transfers are supported. Bursts are supported without special software restrictions. That is, bursts can start at any byte address and end on any byte address and can be of arbitrary length. Also, the arbitration logic insures that the PCI does not monopolize the PCI bus.

As per the PCI specification, the byte enables are allowed to change on each data phase. This has no practical effect on reads, but is supported on writes. The memory addresses linearly increment by 4 on each beat of the PCI burst. All PCI devices must use only linear burst incrementing.

Table 5 shows which CAS# lines are activated when a PCI master writes memory. Note that CAS[0]# refers to byte addresses 0 mod 8, CAS[1]# refers to byte addresses 1 mod 8, etc. For read cycles, eight bytes of memory data are read on each access, but the master receives only the desired 4 bytes. The bytes are read or written to memory independently of BE or LE mode (the endian mode byte swappers are situated between the CPU and the rest of the system, not between the PCI and the rest of the system).

In ECC mode, PCI to memory transactions that result in less than 8-byte writes, cause the memory controller in the 660 Bridge to execute a read-modify-write operation, during which 8 bytes of memory data are read, the appropriate bytes are modified, the ECC byte is modified, and then the resulting 8 bytes are written to memory.

Table 5. Active CAS# Lines - PCI to Memory Writes, BE or LE Mode

PCI_
AD[2]

 Byte Enables BE[ ]#

 Column Address Selects CAS[ ]#
3

 2

 1

 0

 0

 1

 2

 3

 4

 5

 6

 7
0

1

1

1

1

0

1

1

1

0

X

0

1

1

0

1

X

0

1

1

0

0

X

X

0

1

0

1

1

X

0

1

0

1

0

X

X

0

1

0

0

1

X

X

0

1

0

0

0

X

X

X

0

0

1

1

1

X

0

0

1

1

0

X

X

0

0

1

0

1

X

X

0

0

1

0

0

X

X

X

0

0

0

1

1

X

X

0

0

0

1

0

X

X

X

0

0

0

0

1

X

X

X

0

0

0

0

0

X

X

X

X

1

1

1

1

1

1

1

1

1

0

X

1

1

1

0

1

X

1

1

1

0

0

X

X

1

1

0

1

1

X

1

1

0

1

0

X

X

1

1

0

0

1

X

X

1

1

0

0

0

X

X

X

1

0

1

1

1

X

1

0

1

1

0

X

X

1

0

1

0

1

X

X

1

0

1

0

0

X

X

X

1

0

0

1

1

X

X

1

0

0

1

0

X

X

X

1

0

0

0

1

X

X

X

1

0

0

0

0

X

X

X

X

Note:
X = active. Blank = inactive. Byte enables normally represent contiguous addresses. This table shows all cases.

1.3 Bus Arbitration Logic

The reference design uses the Intel SIO as the PCI bus arbiter. The PCI arbiter sees the 660 Bridge as one of several PCI agents. The order of priority for PCI arbitration is programmable, and is initially set to be:

1. (CPUREQ) - 660 Bridge (the SIO normally parks the bus on the 660 Bridge)

2. (REQ1) - PCI slot 2

3. (SIOREQ) - SIO

4. (REQ0) - SCSI

5. (REQ2) - Ethernet

6. (REQ3) - PCI Slot 1.

For more information on arbitration, see the Registers section and the PCI Arbitration Controller section of the SIO data book. See the reference design schematics for the connection of the various PCI requests and grants.

There can be concurrency of cycles on the ISA bus (caused by DMA or ISA masters) with PCI or CPU transactions as long as the ISA bus operations are not forwarded to the PCI bus. Forwarding of ISA bus operations must wait for the ISA bridge to grant the PCI bus access to its ISA interface.

1.4 PCI Configuration Transactions

The preferred method for generating PCI configuration cycles is via the 660 Bridge indexed Bridge Control Registers (BCR). This configuration method is described in Section 4 of the 660 User's Manual. The IDSEL assignment and their respective PCI_AD lines are shown here in Table 6. The addresses used for configuration are assigned as shown.

Table 6. 660 Bridge Address Mapping of CPU Bus Transactions

Device

ID Sel Line

60X Address*

PCI Address

82378ZB PCI to ISA Bridge

A/D 11

8080 08XXh

0080 08XX

53C810 SCSI Controller

A/D 12

8080 10XXh

0080 10XX

PCI Slot 1 (lower)

A/D 13

8080 20XXh

0080 20XX

PCI Slot 2 (upper)

A/D 14

8080 40XXh

0080 40XX

Multiprocessor Interrupt Controller

A/D 15

8080 80XXh

0080 80XX

79C970 Ethernet Controller

A/D 16

8081 00XXh

0081 00XX

Note:
* This address is independent of contiguous I/O mode.

1.4.1 650 Bridge Compatible Method

If it is not possible to use indexed BCRs to generate PCI configuration cycles, they can be generated by an alternate method known as the 650 Bridge compatible method. CPU accesses to the address range 2G+8M to 2G+16M cause the Bridge to arbitrate for the PCI bus and then to execute a type 0 PCI configuration transaction as described in the PowerPC Reference Platform Specification and implemented by the IBM27-82650 PowerPC to PCI Bridge. This is referred to as the 650 compatible configuration method.

1.5 PCI Bus Loading

The reference design motherboard presents 11 to 13 loads to the PCI bus. Two of these, the FLASH/ROM and IDSEL selects, are resistively coupled as recommended in the PCI 2.0 specification to reduce loading. Of the remaining 11 loads, 2 are devices in PCI slots. The remaining 9 loads consist of connectors and PCI devices on the motherboard and riser card. The motherboard and riser card have been designed to allow the timing requirements for 33MHz operation as defined in PCI rev 2.1 if PCI compliant adaptors are installed in both PCI slots. See the Physical Design Guidelines section for more information.