Section 1
ISA and X-Bus

The reference design provides two standard ISA expansion slots via the riser card (see the Riser section for riser card information). The ISA bus is the tertiary or I/O bus for the reference design. It is controlled and interfaced to the PCI bus via an ISA bridge. The reference design uses a buffered subset of the ISA bus, called the X-bus, to interface to various onboard devices.

The Native (Super) I/O controller and the Business Audio controller reside on the ISA bus. For information on these controllers, see the I0/O Subsystems section, and the controller data sheets.

Subsections 1 through 5 describe the operation of the ISA bus.

Subsection 6 gives a functional description of the X-bus.

Subsection 7 describes the X-bus keyboard/mouse controller and registers.

Subsection 8 describes the X-bus real time clock (RTC) and registers.

Subsection 9 describes the X-bus NVRAM and registers.

Subsection 10 describes the X-bus presence detect registers.

For information on X-bus registers that are internal to the system EPLD, see the EPLD section.

For a complete listing of the ISA/X-bus registers, see the Registers section.

For more information on ISA interrupts and MPIC, see the Exceptions section. Also see the MPIC data sheet.

Also see the Intelt 82378ZB data book.

1.1 The ISA Bridge

The ISA bridge function is provided by an Intelt 82378ZB chip (SIO). It provides a PCI to ISA bus bridge, with the following major functions:

S 8/16 bit ISA devices

S 24 bit addressing on ISA

S Partially decodes native I/O addresses

S Unclaimed PCI memory address below 16MB forwarded to the ISA bus

S Unclaimed PCI I/O address below 64K forwarded to the ISA bus

S Powers up to an open condition (i.e., cycles may be passed to the ISA bus)

S Generates ISA clock, with a programmable divide ratio of three or four

S Allows ISA mastering and has programmable decodes that map ISA memory cycles to the PCI bus

S 32-bit posted memory write data buffer (no I/O buffering)

S Function of two 83C37s with 32-bit extensions

S Supports 8-bit or 16-bit devices on the ISA bus

S Supports 32-bit addressing for ISA to PCI memory transfers

S 8-byte bidirectional buffer for DMA data

1.2 Address Ranges

The ISA bus address ranges which may be separately enabled in the ISA bridge for forwarding to the PCI bus are:

If an ISA DMA produces an address in the 0-16M range and this address is enabled in the ISA bridge for forwarding to the PCI, the ISA bridge will initiate a PCI transaction which the 660 bridge will, in all cases (see ISA Busmasters and IGN_PCIAD31 in the ISA and X-Bus section), forward to system memory. Do not enable other PCI agents to claim PCI memory transactions in this range.

The 660 bridge actively decodes and claims these ISA master originated cycles on the PCI bus. It does not use subtractive decoding. Any other PCI agent that attempts to claim these transactions will create a bus contention. Thus ISA masters can only access other ISA devices or system memory. They may not access PCI devices.

The software must not map any PCI memory at PCI addresses which ISA masters can create (those addresses from 0 to 16M which are programmed for forwarding from ISA to PCI). In that case, an ISA transaction forwarded to the PCI bus would be claimed both by the 660 Bridge and by the PCI memory device. Alternatively stated, ISA masters are not allowed to create accesses to system memory using any address from 0 to 16M that is mapped to a PCI device, such as video. Also see ISA Busmasters and IGN_PCIAD31 in the ISA and X-Bus section.

1.3 ISA Bus Concurrency

ISA bus cycles which are not enabled for forwarding, including the hole, remain on the ISA bus. That is, DMA or ISA bus master cycles on the ISA bus can run concurrently with PCI or CPU cycles.

1.4 ISA Busmasters and IGN_PCI_AD31

The ISA bridge supports ISA bus masters. System memory accesses from an ISA bus master are designed to be mapped to the 0 to 16M range, and the ISA bridge forwards them to the PCI bus at the same range, which is not compliant to the PowerPC Reference Platform specification. Other PCI to system memory accesses, however, are compliantly mapped to the 2G to 4G range (for system memory address range from 0 to 2G). In some architectures this problem is handled by using the ISA_MASTER# signal, which is active during the ISA bus master operation.

However, the ISA bridge allows ISA masters to run posted writes to system memory without latching in the accompanying ISA_MASTER# signal. In this situation, the ISA_MASTER# signal is no longer synchronized to the ISA bus master operation.

To overcome this challenge, the 660 Bridge does not use the ISA_MASTER# signal. Instead, it detects PCI memory transactions that are initiated by the ISA bridge. The reference design ANDs together GNT0#, GNT1#, GNT2#, and GNT3# (all of the PCI grants except the ISA bridge internal grant) to generate IGN_PCI_AD31, which is active high during the address phase of any PCI transaction that is not initiated by one of the four possible PCI agents (besides the 660 bridge and the ISA bridge). If the PCI transaction was not initiated by the 660 bridge, and if it is a memory transaction, then the 660 bridge knows that it is a system memory transaction initiated on the PCI bus by the SIO. It then assumes that the transaction is on behalf of an ISA bus master, and so forwards it to the correct system memory address in the 0 to 16M range.

As a consequence of this design, the ISA bridge must be programmed to map ISA DMA (that is bound for system memory) to a PCI memory transaction using the 0 to 2G address range, rather than the apparently correct 2G to 4G range. Since the DMA-sourced PCI transaction also causes IGN_PCI_AD31 to be asserted during the address phase of a PCI transaction initiated by the ISA bridge, the 660 bridge will not do the usual inversion of the highest order address bit, but will forward the transaction to system memory in the 0 to 2G range.

Another consequence of the design is that the ISA bridge can not initiate peer to peer PCI memory transactions, because no matter what the PCI address is, it will be claimed by the 660 bridge (if the address is that of a populated memory location) and mapped to system memory, possibly causing various inappropriate results. Also see Address Ranges in the ISA and X-Bus section.

These are the only limitations on the normal operation of the ISA bridge that are caused by the IGN_PCI_AD31 design, and there are no implications for other PCI or ISA agents, which are totally unaffected by the situation.

1.5 DMA

The DMA controller in the ISA bridge consists of two 82C37A DMA controllers with 32-bit addressability extensions and enhanced functionality. The DMA request/grant lines are connected on the reference design as shown in Table 1.

Table 1. DMA Assignments

DMA Channel

Assignment or Connection

0

ISA slots, Audio (note 2), EPP (note 1)

1

ISA slots, Audio (note 2), EPP (note 1)

2

ISA slots, Floppy Disk Controller (SuperI/O)

3

ISA slots, Audio (note 2), EPP (note 1)

4

Cascade in

5

ISA slots, EPP (note 1)

6

ISA slots

7

ISA slots

Notes:

  • The Enhanced Parallel Port (EPP) feature of the National 87332 SuperI/O chip can be mapped to DMA channel 0, 1, 3, or 5 using the control mechanism provided in Port 87C, the System Control Port of the system EPLD.
    Port 87Cbits [2:0]
    0 x x No DMA
    1 0 0 Channel 0
    1 0 1 Channel 1
    1 1 0 Channel 3
    1 1 1 Channel 5
  • The Audio DMA channels are selected within the Crystal CS4332 controller. The DMA channels are assigned as follows:
    CS4232 DMA Channel System DMA Channel
    A 0
    B 1
    C 3

    • 1.5.1 Supported DMA Paths

    DMA operations can be performed only:

    The DMA source device can be located on the ISA or X-bus. If the DMA target is ISA memory mapped, it can also reside on the X-bus.

    1.5.2 DMA Timing

    The DMA controller runs compatible cycles for all ISA to ISA DMA transfers. Type A, type B and type F timing is available only for ISA I/O to system memory (via the PCI) DMA transfers.

    1.5.3 Scatter-Gather

    The reference design permits the use of independent scatter-gather (SG) operations on DMA channels 0-3 and 5-7. This operation chains together a number of DMA transfers to different memory locations so that they appear as one DMA transfer. The SG command, descriptor table, and status registers are relocatable via a configuration register in the ISA bridge. The termination of an operation may be signaled to the software by configuring any (or all) of the SG channels to signal end of process (aka Terminal Count) to the DMA device. It is also possible to use IRQ13 to signal the end of DMA, but this is not recommended. See Scatter/Gather (SG) Interrupts in the Exceptions section.

    1.6 X-Bus

    The X-bus is a utility bus, an 8 bit buffered subset of the ISA bus that is implemented on the reference board to support motherboard native I/O devices and motherboard registers. The address range of the X-bus is a subset of the ISA bus address range. Figure 1 shows the ISA bridge, a PCI agent which sources the ISA and X-busses. The X-bus data transceiver is controlled by the ISA bridge via XDIR and XDEN#. The ISA bridge also generates the X-bus control signals and partial ISA bus address decode signals, which the system EPLD uses to decode the address strobes for ISA registers.



    Reference design X-bus registers are located in the following areas:

    Additional ISA bus registers are located in the Business Audio and Super I/O controllers. Certain ISA bridge registers are also mapped to ISA space.

    1.7 Keyboard/Mouse Controller

    The reference design uses an Intel 8042AH as a keyboard and mouse controller. It resides on the X-bus. The code used is the same version as is used in IBM Personal System/2 machines. This microcode may differ from other 8042-type keyboard controllers. These differences are usually only significant when porting AIX to the system (for more information contact your IBM technical representative). See the controller data sheet for more information. This device contains several registers.

    1.7.1 Keyboard/Mouse Control Registers

    ISA Port 0060

    		Read/Write

    		Reset to n/a

    ISA Port 0062

    		Read/Write

    		Reset to n/a

    ISA Port 0064

    		Read/Write

    		Reset to n/a

    ISA Port 0066

    		Read/Write

    		Reset to n/a

    This register set is located inside the keyboard/mouse controller. See the keyboard/mouse controller data sheet for details. The system EPLD asserts KYBD_CS# to access these ports.



    1.8 Real Time Clock (RTC)

    The reference design uses a Dallas Semiconductort DS1385S to provide the real time clock (TOD or RTC) function. This device is PC compatible and resides on the X-bus. It features an additional 4K of NVRAM and a replaceable battery. This device contains several registers. See the data sheet for more information.

    The RTC section of the DS1385S contains 64 8-bit registers. There are 50 bytes of user RAM, 10 bytes of time, calender, and alarm data, and 4 bytes of control and status information. Access to RTC registers can be accomplished by writing to the following registers in the given sequence:

    1.8.1 RTC Address and NMI Enable Register

    ISA Port 0070

    		Write Only

    		Reset to n/a

    This register is shared by the RTC and the ISA bridge.



    Bit 6:0 RTC Internal byte address (1 of 64). The SIO ignores these bits during writes and does not drive them during reads. The SIO decodes accesses to this port internally.

    Bit 7 NMI Enable. The SIO uses this bit to enable its NMI output. The RTC ignores the bit on writes and does not drive the bit on reads. The system EPLD asserts RTC_ALE to the RTC to access these bits of the port.

    1.8.2 RTC Data Register

    ISA Port 0071

    		Read/Write

    		Reset to n/a

    This register is used to access the registers within the RTC. Reads and writes to this port access the internal RTC register pointed to by the RTC Address and NMI Enable register. This register is located inside the RTC. The system EPLD asserts RTC_WR# to write to this register, and RTC_RD# to read the register.



    1.9 Non-Volatile RAM (NVRAM)

    The system NVRAM is locate inside the RTC package. The DS1385S has 4Kx8 of SRAM. The NVRAM is accessed by the following sequence of operations:

    1.9.1 NVRAM Address Register Low

    ISA Port 0074

    		Write Only

    		Reset n/a

    This register contains the lower 8 bits of the 12 bit NVRAM internal address. This register is located inside the RTC. The system EPLD decodes accesses to this register by asserting AS0#.



    1.9.2 NVRAM Address Register High

    ISA Port 0075

    		Write Only

    		Reset n/a

    This register contains the lower 8 bits of the 12 bit NVRAM internal address. This register is located inside the RTC. The system EPLD decodes accesses to this register by asserting AS1#.



    1.9.3 NVRAM Data Register

    ISA Port 0077

    		Read/Write

    		Reset to n/a

    This register is used to access the registers within the NVRAM. Reads and writes to this port access the internal NVRAM byte pointed to by the NVRAM address registers. This register is located inside the RTC. The system EPLD asserts NVRAM_WR# to write to this register, and NVRAM_RD# to read the register.



    1.10 Motherboard Presence Detect Registers

    The following registers are located on the motherboard. They are generally implemented as shown in Figure 1 and Figure 2.



    1.10.1 Floppy Media Sense ID

    ISA Port 03F3

    		Read Only

    		Reset n/a

    The reference design uses U27 to buffer the Floppy Media Sense bits from the floppy drive connector onto the X-bus SD[7:4]. The system EPLD asserts RD_3F3# to read this register.

    The SuperI/O chip also decodes reads to 03F3, and should be configured to respond only on bits SD[3:0].



    Bit 1:0 Tape Select [1:0] - Driven by the FDC in the SuperI/O.

    Bit 3:2 Reserved

    Bit 5:4 Floppy Drive ID [1:0] - driven by U27.

    Bit 7:6 Floppy Media Sense [1:0] - driven by U27.

    1.10.2 Equipment Presence Register

    ISA Port 080C

    		Read Only

    		Reset n/a

    The reference design uses U23 to buffer the equipment presence detect bits onto the X-bus. The system EPLD asserts EQP_PRSNT_RD# to read this register.



    Bit 4 PCI Slot 1 PD bit. 0 means there is a PCI device in slot 1.

    Bit 5 PCI Slot 2 PD bit. 0 means there is a PCI device in slot 2.

    Bit 6 SCSI Fuse Good. 1 means the fuse is intact.

    Bit 7 Reserved.

    1.10.3 L2 ID Register

    ISA Port 080D

    		Read Only

    		Reset n/a

    The reference design supports a 182 pin tag/SRAM module in the L2 slot. The L2 ID register (U23) is used to buffer the L2 slot presence detect bits onto the X-bus. The system EPLD asserts CACHE_PD_RD# to read this register. Table 2 shows the encoding of these bits.



    Table 2. L2 Cache SRAM/TagRAM PD Table

    PD3

    		 PD2

    		 PD1 *

    		 PD0 *

    		 Description
    0

    		0

    		0

    		0

    		Burst

    		256K

    		No Parity

    0

    		0

    		0

    		1

    		Burst

    		512K

    		No Parity

    0

    		0

    		1

    		0

    		Burst

    		1M

    		No Parity

    0

    		0

    		1

    		1

    		Reserved

    0

    		1

    		0

    		0

    		Burst

    		256K

    		Parity

    0

    		1

    		0

    		1

    		Burst

    		512K

    		Parity

    0

    		1

    		1

    		0

    		Burst

    		1M

    		Parity

    0

    		1

    		1

    		1

    		Reserved

    1

    		0

    		0

    		0

    		Async

    		256K

    		No Parity

    1

    		0

    		0

    		1

    		Async

    		512K

    		No Parity

    1

    		0

    		1

    		0

    		Async

    		1M

    		No Parity

    1

    		0

    		1

    		1

    		Reserved

    1

    		1

    		0

    		0

    		Async

    		256K

    		Parity

    1

    		1

    		0

    		1

    		Async

    		512K

    		Parity

    1

    		1

    		1

    		0

    		Async

    		1M

    		Parity

    1

    		1

    		1

    		1

    		No L2 card or serial EEPROM

    Note:
    *     When a serial ROM is installed, PD[1:0] become IDS_DATA and IDS_CLK.

    1.10.4 Motherboard ID Register

    ISA Port 0852

    		Read Only

    		Reset n/a

    The reference design uses U29 to buffer the motherboard ID bits onto the X-bus. The system EPLD asserts PLANAR_ID_RD# to read this register.



    Table 3. Motherboard ID Encoding

    Motherboard
    ID[7:0]

    		Schematic

    5A

    		PowerPC 604 SMP
    Reference Design-Preliminary

    other

    		Reserved

    1.10.5 CPU ID Registers

    ISA Port 0866

    		Read Only

    		Reset n/a

    ISA Port 0867

    		Read Only

    		Reset n/a

    The reference design supports two CPU slots. The CPU ID registers are used to read the presence detect bits of these slots. The system EPLD asserts PROC1_PD_RD# to enable U28 to drive the PD bits from CPU slot 1 onto the X-bus. The system EPLD asserts PROC2_PD_RD# to enable U56 to drive the PD bits from CPU slot 2 onto the X-bus.

    A shown in Table 4, the CPU_PD bits report information about the CPU, and the CPU_L2_PD bits report information about any L2 which might be on the CPU card. These L2 PD bits are not the same as the L2 PD bits associated with the L2 slot.



    Table 4. CPU_PD Bits
    CPU_PD0

    		 CPU_PD1

    		 CPU_PD2

    		 CPU_PD3

    		 CPU_L2_ PD0

    		 CPU_L2_ PD1

    		 Description
    0

    		0

    		0

    		0

    		x

    		x

    		No CPU

    0

    		0

    		0

    		1

    		x

    		x

    		100 MHz CPU

    0

    		0

    		1

    		0

    		x

    		x

    		120 MHz CPU

    0

    		0

    		1

    		1

    		x

    		x

    		132 MHz CPU

    0

    		1

    		0

    		0

    		x

    		x

    		150 MHz CPU

    0

    		1

    		0

    		1

    		x

    		x

    		167 MHz CPU

    0

    		1

    		1

    		0

    		x

    		x

    		180 MHz CPU

    0111 thru 1110

    		x

    		x

    		Reserved

    1

    		1

    		1

    		1

    		x

    		x

    		No CPU card present.

    x

    		x

    		x

    		x

    		0

    		0

    		Reserved

    x

    		x

    		x

    		x

    		0

    		1

    		TBD

    x

    		x

    		x

    		x

    		1

    		0

    		TBD

    x

    		x

    		x

    		x

    		1

    		1

    		Serial ROM or no L2.

    Note:
    For information on the L2 serial ROM option, see L2 Cache ID ROM Signaling Interface in the CPU Bus section.

    1.10.6 DRAM ID Registers

    ISA Port 0880 thru 0883

    		Read Only

    		Reset n/a

    The reference design supports 72 pin, 4-byte wide industry standard parity DRAM modules (SIMMs). The DRAM ID registers are buffers that drive the SIMM presence detect bits onto the X-bus. Figure 3 shows how the registers are accessed. Table 5 shows the bit fields that correspond to each SIMM. Table 6 shows the encoding of the SIMM ID bits.



    Table 5. DRAM PD Registers

    Bank

    		Buffer

    		SIMM

    		MPD[]

    		Port

    		Bits

    0

    		U58

    		0

    		3:0

    		0880

    		3:0

    1

    		7:4

    		7:4

    1

    		U52

    		2

    		11:8

    		0881

    		3:0

    3

    		15:12

    		7:4

    2

    		U54

    		4

    		19:16

    		0882

    		3:0

    5

    		23:20

    		7:4

    3

    		U53

    		6

    		27:24

    		0883

    		3:0

    7

    		31:28

    		7:4



    Table 6. SIMM Definition

    SIMM ID [3:0]

    		 SIMM Type

    		 SIMM Speed
    1111

    		Absent

    		-

    1111

    		8 M

    		60 ns

    1110

    		16 M

    		60 ns

    1101

    		32 M

    		60 ns

    1100

    		4 M

    		60 ns

    1011

    		8 M

    		70 ns

    1010

    		16 M

    		70 ns

    1001

    		32 M

    		70 ns

    1000

    		4 M

    		70 ns

    To distinguish between no SIMM present and an 8M, 60ns SIMM, a write-read verify test can be performed.