W International Business Machines Corporation, 1995. Printed in the United States of America 12/95. All Rights reserved.
IBM Microelectronics, PowerPC, PowerPC 603e, PowerPC 604, RISCWatch, and AIX are trademarks of the IBM corporation. IBM and the IBM logo are registered trademarks of the IBM corporation. Other company names and product identifiers are trademarks of the respective companies.
This document contains information which is subject to change by IBM without notice. IBM assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for use in implantation or other direct life-support applications where malfunction may result in physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT.
Contacts
ESD Warning
The motherboard, CPU, and memory cards contain CMOS devices which are very susceptible to ElectroStatic Discharge (ESD). DO NOT remove them from the antistatic bags until you have connected yourself to an acceptable ESD grounding strap. Work in a static free environment and be sure any person or equipment coming into contact with the cards does not have a static charge. The cards are particularly susceptible until they are placed in a properly designed enclosure. Bench work should be done by persons connected to ESD grounding straps.
IBM POWERPC 604TM SMP REFERENCE DESIGN AGREEMENT
BEFORE READING THE REST OF THE DOCUMENT, YOU SHOULD CAREFULLY READ THE FOLLOWING TERMS AND CONDITIONS. OPENING THE PACKAGE INDICATES YOUR ACCEPTANCE OF THESE TERMS AND CONDITIONS. IF YOU DO NOT AGREE WITH THEM, YOU SHOULD PROMPTLY RETURN THE PACKAGE UNOPENED TO YOUR IBM SALES OFFICE.
International Business Machines Corporation ("IBM") agrees to provide you a PowerPC 604 SMP Reference Design (Reference Design) in return for your promise to use reasonable efforts to develop a system based on the technology in the Reference Design. The Reference Design contains documentation and software listed below:
Documentation
PowerPC 604 SMP Reference Design Technical Specification
PowerPC 604 RISC Microprocessor Hardware Specification
IBM PowerPC 604 SMP Reference Board Design Files (on 8mm tape)
IBM PowerPC 604 SMP Reference Board Mfg. Data Files (in Gerber format)
IBM14N1372 Data Sheet
IBM11D4360B Data Sheet
Selected data sheets from other manufacturers (included with their permission).
LICENSE TO SOFTWARE
The software is licensed not sold. IBM, or the applicable IBM country organization, grants you a license for the software only in the country where you received the software. Title to the physical software and documentation (not the information contained in such documentation) transfers to you upon your acceptance of these terms and conditions. The term "software" means the original and all whole or partial copies of it, including modified copies or portions merged into other programs. IBM retains title to the software. IBM owns, or has licensed from the owner, copyrights to the software provided under this agreement. The terms of this Agreement apply to all of the hardware, software and documentation provided to you as part of the Reference Design.
With regard to the software provided hereunder, it is understood and agreed that you intend to use the software solely for the purpose of designing PowerPCTM compatible products, testing your designs, and making your own independent determination of whether you wish to eventually manufacture PowerPC compatible products commercially. In accordance with this understanding, IBM hereby grants you the rights to: a) use, run, and copy the software, but only make such number of copies and run on such number of machines as are reasonably necessary for the purpose of designing PowerPC compatible products and testing such designs; and b) copy the software for the purpose of making one archival or backup copy.
With regard to any copy made in accordance with the foregoing license, you must reproduce any copyright notice appearing thereon. With regard to the software provided hereunder, you may not: a) use, copy, modify or merge the software, except as provided in this license; b) reverse assemble or reverse compile it; or c) sell, sublicense, rent. lease, assign or otherwise transfer it. In the event that you no longer wish to use the software, you will return it to IBM.
LICENSE TO DESIGN DOCUMENTATION
With regard to the design documentation provided hereunder, it is understood that you intend to use such documentation solely for the purpose of designing your own PowerPC compatible products, testing your designs, and making your own independent determination of whether you wish to eventually manufacture PowerPC compatible products commercially. In accordance with this understanding, IBM hereby grants you the right to: a) use the design documentation for the purpose of designing PowerPC compatible products and testing such designs; b) make derivative works of the design documentation for the purpose of designing PowerPC compatible products, and testing such designs; and c) make copies of the design documentation and any such derivative works, but only such numbers as are reasonably necessary for designing PowerPC compatible products and testing such designs.
With regard to any copy made in accordance with the forgoing license, you must reproduce any copyright notice appearing thereon. With regard to the design documentation provided hereunder, you may not: a) copy, modify, or merge the design documentation as provided in this license; or b) sell, sublicense, rent, lease, assign, or otherwise transfer it.
In the event you no longer wish to use the design documentation or any derivative versions thereof, you must return them to IBM.
DISCLAIMER OF WARRANTY
IBM does not represent or warrant that the Reference Design (which may contain prototype items): a) meets any particular requirements; b) operates uninterrupted; c) is error free; or d) is non-infringing of any patent, copyright, or other intellectual property right of any third party. IBM makes no representation or warranty regarding the performance or compatibility that may be obtained from the use of the Reference Design or that the Reference Design is adequate for any use. The Reference Design may contain errors and may not provide the level of completeness, functionality, support, performance, reliability, or ease of use available with other products, whether or not similar to the Reference Design. IBM does not represent or warrant that errors or other defects will be identified or corrected.
THE REFERENCE DESIGN IS PROVIDED "AS IS" WITH ALL FAULTS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE REFERENCE DESIGN IS WITH YOU.
Some jurisdictions do not allow exclusion of implied warranties, so the above exclusions may not apply to you.
LIMITATION OF REMEDIES
IBM's entire cumulative liability and your exclusive remedy for damages for all causes, claims or actions wherever and whenever asserted relating in any way to the subject matter of this agreement including the contents of the Reference Design and any components thereof, is limited to twenty five thousand dollars ($25,000.00) or its equivalent in your local currency and is without regard to the number of items in the Reference Design that caused the damage. This limitation will apply, except as otherwise stated in this Section, regardless of the form of the action, including negligence. This limitation will not apply to claims by you for bodily injury or damages to real property or tangible personal property. In no event will IBM be liable for any lost profits, lost savings, or any incidental damages or economic consequential damages, even if IBM has been advised of the possibility of such damages, or for any damages caused by your failure to perform your responsibilities. In addition, IBM will not be liable for any damages claimed by you based on any third party claim. Some jurisdictions do not allow these limitations or exclusions, so they may not apply to you.
RISK OF LOSS
You are responsible for all risk of loss or damage to the Reference Design upon its delivery to you.
IBM TRADEMARKS AND TRADE NAMES
This Agreement does not give you any rights to use any of IBM's trade names or trademarks. You agree that should IBM determine that any of your advertising, promotional, or other materials are inaccurate or misleading with respect to IBM trademarks or trade names, that you will, upon written notice from IBM, change or correct such materials at your expense.
NO IMPLIED LICENSE TO IBM INTELLECTUAL PROPERTY
Notwithstanding the fact that IBM is hereby providing design information for your convenience, you expressly understand and agree that, except for the rights granted under the sections above, no right or license of any type is granted, expressly or impliedly, under any patents, copyrights, trade secrets, trademarks, or other intellectual property rights of IBM. Moreover, you understand and agree that in the event you wish to be granted any license beyond the scope of the expressly stated herein, you will contact IBM's Intellectual Property Licensing and Services Office (currently located at 500 Columbus Avenue, Thornwood, N.Y.), or such other IBM offices responsible for the licensing of IBM intellectual property, when you seek the license.
YOUR ASSUMPTION OF RISK
You shall be solely responsible for your success in designing, developing, manufacturing, distributing, and marketing any product(s), or portion(s), where use of all or any part of the Reference Design is involved. You are solely responsible for any claims, warranties, representations, indemnities and liabilities you undertake with your customers, distributors, resellers or others, concerning any product(s) or portion(s) of product(s) where use of all or any part of the Reference Design is involved. You assume the risk that IBM may introduce other Reference Designs that are somehow better than the Reference Design which is the subject of this Agreement. Furthermore, you accept sole responsibility for your decision to select and use the Reference Design; for attainment or non-attainment of any schedule, performance, cost, reliability, maintainability, quality, manufacturability or the like, requirements, or goals, self-imposed by you or accepted by you from others, concerning any product(s) or portion(s) of product(s), or for any delays, costs, penalties, charges, damages, expenses, claims or the like, resulting from such non-attainment, where use of all or any part of the Reference Design is involved.
GENERAL
In the event there is a conflict between the terms of this Agreement and the terms printed or stamped on any item or any ambiguities with respect thereto, including documentation, contained in the Reference Design, the terms of this Agreement control to the extent IBM is afforded greater protection thereby. IBM may terminate this Agreement if you fail to comply with the terms and conditions of this Agreement. Upon termination of this Agreement, you must destroy all copies of the software and documentation. You are responsible for payment of any taxes, including personal property taxes, resulting from this Agreement. Neither party may bring an action hereunder, regardless of form, more than one (1) year after the cause of the action arose. If you acquired the Reference Design in the United States, this Agreement is governed by the laws of the State of New York. In the event of litigations, trial shall be in New York without a jury. If you acquired the Reference Design in Canada, this Agreement is governed by the laws of the Province of Ontario; otherwise, this Agreement is governed by the laws of the country in which you acquired the Reference Design. All obligations and duties which, by their nature, survive termination or expiration of this Agreement, shall remain in effect beyond termination or expiration of this Agreement, and shall bind IBM, you and your successors and assigns. If any section or paragraph of this Agreement is found by competent authority to be invalid, illegal or unenforceable in any respect for any reason, the validity, legality, and enforceability of any such section or paragraph in every other respect, and the remainder of this Agreement, shall continue in effect so long as it still expresses the intent of the parties. If the intent of the parties cannot be preserved, the parties will attempt to renegotiate this Agreement and failing renegotiation, this Agreement will then be terminated. The headings in this Agreement shall not affect the meaning or interpretation of this Agreement in any way. No failure by IBM in exercising any right, power or remedy under this Agreement shall serve as a waiver of any such right, power or remedy. Neither this Agreement nor any activities hereunder will impair any right of IBM to develop, manufacture, use or market, directly or indirectly, alone or with others, any products or services competitive with those offered or to be offered by you; nor will this Agreement or any activities hereunder require IBM to disclose any business planning information to you. You agree to comply with all applicable government laws and regulations. Any changes to this Agreement must be in writing and signed by the parties.
NOTICE
The MPIC chip referenced in this document is not currently generally available from IBM. The Verilog source of MPIC is available from IBM under license at no charge. Contact your IBM representative for details.
Section 1 Introduction 23
1.1 IBM Reference Products 23
1.1.1 Reference Design 23
1.1.2 Reference Boards and Systems 23
1.1.3 Reference Firmware 23
1.2 Purpose 24
1.3 Differences Between Releases 1.0, 3.0 and 4.0 24
1.4 Reference Design Overview 24
1.4.1 Processor Cards 27
1.4.2 Other CEC Functions 27
1.4.3 IBM27-82660 Bridge 27
1.4.4 L2 Cache 27
1.4.5 System Memory 27
1.4.6 PCI Bus 28
1.4.7 SCSI Controller 28
1.4.8 Network Support AMD AM79C970A (Ethernet) 28
1.4.9 Multi-Processor Interrupt Controller (MPIC) 28
1.4.10 Flash ROM 28
1.4.11 PCI/ISA Bridge Chip 29
1.4.12 Business Audio 29
1.4.13 Native I/O Controller National PC87332 Super I/O 30
1.4.14 X Bus 30
1.4.15 Time of Day Clock 30
1.4.16 PS/2 Compatible Keyboard/Mouse Controller 30
1.4.17 System I/O EPLD 30
1.4.18 System Clocks 30
1.5 Quickstart Peripheral List 31
Section 2 CPU Bus 33
2.1 CPU Busmasters 33
2.1.1 CPU Bus Arbitration 34
2.1.2 Fast L2/Data Streaming Mode (No-DRTRY#) 34
2.1.3 CPU Bus Frequency 34
2.1.4 Bi-Endian Mode Operation 34
2.2 System Response by CPU Bus Transfer Type 35
2.3 System Response by CPU Bus Address Range 36
2.3.1 Address Mapping for Contiguous I/O 37
2.3.2 Address Mapping for Non-Contiguous I/O 38
2.3.3 PCI Final Address Formation 39
2.4 CPU to Memory Transfers 39
2.4.1 LE Mode 39
2.5 CPU to PCI Transactions 39
2.5.1 CPU to PCI Read 40
2.5.2 CPU to PCI Write 40
2.5.2.1 Eight-Byte Writes to the PCI (Memory and I/O) 40
2.5.3 CPU to PCI Memory Transactions 40
2.5.4 CPU to PCI I/O Transactions 40
2.5.5 CPU to PCI Configuration Transactions 40
2.5.6 CPU to PCI Interrupt Acknowledge Transaction 41
2.5.7 PCI Locks and CPU Reservations 41
2.6 CPU to ROM Transfers 41
2.6.1 CPU to ROM Read 42
2.6.2 CPU to ROM Write 42
2.6.2.1 ROM Write Protection 42
2.6.3 CPU to BCR Transfers 43
2.7 CPU Card Interface (CPU Slot) 43
2.7.1 CPU Slot Signal Descriptions 44
2.7.2 CPU Slot DC Characteristics 56
2.7.3 CPU Slot AC Timing 56
2.7.4 CPU Slot Power Supplies 57
2.7.5 CPU Slot Thermal Envelope 57
2.7.6 CPU Slot Card Connector 58
2.7.7 Auxiliary CPU Slot Connectors 63
2.8 L2 Tag/SRAM Interface (L2 Slot) 64
2.8.1 L2 Slot ID ROM 64
2.8.1.1 L2 Cache ID ROM Signaling Interface 66
2.8.2 L2 Slot Signal Descriptions 67
2.8.3 L2 Slot DC Characteristics 71
2.8.4 L2 Slot AC Timing 72
2.8.5 L2 Slot Power Supplies 72
2.8.6 L2 Slot Thermal Envelope 73
2.8.7 L2 Slot Dual Voltage Capability 73
2.8.8 L2 Slot Connector 74
2.8.9 L2 Slot Pin Assignments 75
2.9 JTAG/RISCWatch Interface 78
2.10 Electrical Model of Major Signal Groups 79
2.10.1 Motherboard Electrical Model 79
2.10.2 CPU Card and L2 Card Interface Models 80
2.10.3 CPU Card Model 80
2.10.4 L2 Card Model 80
2.10.5 660 Bridge Electrical Model 80
2.10.6 Model Building 81
Section 3 Endian Mode Considerations 83
3.1 What the 604 CPU Does 84
3.1.1 The 604 Address Munge 84
3.1.2 The 604 Data Shift 84
3.2 What the 660 Bridge Does 84
3.2.1 The 660 Bridge Address Unmunge 84
3.2.2 The 660 Bridge Data Swapper 84
3.3 Bit Ordering Within Bytes 86
3.4 Byte Swap Instructions 87
3.5 604 CPU Alignment Exceptions In LE Mode 87
3.6 Single-Byte Transfers 88
3.7 Two-Byte Transfers 92
3.8 Four-Byte Transfers 94
3.9 Three byte Transfers 96
3.10 Instruction Fetches and Endian Modes 97
3.11 Changing BE/LE Mode 98
3.12 Summary of Bi-Endian Operation and Notes 100
Section 4 CPU Card 101
4.1 Major Components 102
4.1.1 PowerPC Processor 102
4.1.2 JTAG/RISCWatch Interface 102
4.1.3 J2 Auxiliary Test Connector 102
4.1.4 Fansink 103
4.2 Configuration Options 104
4.2.1 Bus Clock Skew Circuit 104
4.2.2 2.5v Power Supply 104
4.2.3 Presence Detect Bits 104
4.2.4 DRVMOD Bits 104
4.2.5 Additional Bits 104
4.3 Electrical and Thermal Requirements 105
4.3.1 Absolute Maximum Ratings 105
4.3.2 DC Specifications 105
4.3.3 Thermal 106
4.3.4 AC Timing Requirements 106
4.4 Electrical Model of Major Signal Groups 107
4.5 CPU Card Slot Connector 108
4.5.1 Pin Definitions 108
Section 5 DRAM and ROM 113
5.1 DRAM 113
5.1.1 Memory Controller (DRAM) 113
5.1.2 Organization 114
5.1.3 Refresh 115
5.1.4 DRAM Presence Detection 116
5.1.5 DRAM Bank Rules 116
5.2 ROM 116
5.2.1 PCI Bus ROM 116
5.2.2 Remote ROM 116
5.2.3 ROM Read, Write, and Write Protect 116
Section 6 Exceptions 117
6.1 Interrupts 117
6.1.1 PCI interrupt handling 118
6.1.2 ISA interrupt handling 118
6.1.3 CPU to CPU Interrupt Handling 119
6.1.4 PCI Interrupt Assignments 119
6.1.5 ISA Interrupt Assignments 120
6.1.5.1 Scatter/Gather (SG) Interrupts 121
6.1.6 SCSI Bus Interrupts 121
6.1.7 MCP# Considerations 121
6.1.8 SMI# Considerations 121
6.2 Resets 122
6.2.1 HRESET# Logic 122
6.2.1.1 JTAG Interface Hard Resets 122
6.2.1.2 HRESET PAL Equations 123
6.2.2 SRESET Logic 125
6.2.3 SRESET PAL equations 126
6.3 SMP Reset Considerations 128
6.3.1 Hard Reset 129
6.3.1.1 Hard Reset Phase 1 129
6.3.1.2 Hard Reset Phase 2 130
6.3.1.3 Hard Reset Phase 3 130
6.3.2 Soft Reset 131
6.4 Error Handling 132
6.4.1 Data Error Checking 132
6.4.1.1 CPU to Memory Writes 132
6.4.1.2 CPU to Memory Reads 132
6.4.1.3 PCI to Memory Parity Errors 132
6.4.1.4 CPU to PCI Transaction Data Parity Errors 133
6.4.2 Illegal CPU cycles 133
6.4.3 SERR, I/O Channel Check, and NMI Logic 133
6.4.4 Out of Bounds PCI Memory Accesses 133
6.4.5 No Response on CPU to PCI Cycles - Master Abort 133
6.4.6 CPU to PCI Cycles That Are Target Aborted 134
6.4.7 Error Status Registers 134
6.4.8 Reporting Error Addresses 134
6.4.9 Errant Masters 134
6.4.10 Special Events Not Reported as Errors 135
Section 7 Clocks 137
7.1 CPU Clocks 137
7.1.1 CPU Card Clock Repeater 138
7.1.2 CPU Clock Physical Design Rules 138
7.2 CPU Clock Control Logic 139
7.2.1 Clock Logic Input - J17 139
7.2.1.1 Clock Logic Input - CPU Slot PD Bits 140
7.2.1.2 Clock Logic Output - CPU Bus Clock Frequency Select 140
7.2.1.3 Clock Logic Output - 604 PLL Configuration 140
7.2.1.4 Clock Logic Transfer Function 140
7.2.2 Frequency Select PAL Equations 142
7.2.3 Clock Freezing 143
7.3 PCI Clocks 144
7.3.1 PCI Bus speed Selection 144
7.4 ISA Bus Clock 144
7.5 Oscillators, Crystals, and Clocks 144
Section 8 PCI Bus 145
8.1 PCI Transaction Decoding 146
8.1.1 PCI Transaction Decoding By Bus Command 146
8.1.2 PCI Memory Transaction Decoding By Address Range 147
8.1.3 PCI I/O Transaction Decoding 148
8.1.4 ISA Master Considerations 148
8.2 PCI Transaction Details 149
8.2.1 Bus Snooping on PCI to Memory Cycles 149
8.2.2 PCI Peer to PCI Peer Transactions 149
8.2.3 PCI to System Memory Transactions 149
8.3 Bus Arbitration Logic 151
8.4 PCI Configuration Transactions 151
8.4.1 650 Bridge Compatible Method 151
8.5 PCI Bus Loading 151
Section 9 ISA and X-Bus 153
9.1 The ISA Bridge 154
9.2 Address Ranges 154
9.3 ISA Bus Concurrency 155
9.4 ISA Busmasters and IGN_PCI_AD31 155
9.5 DMA 156
9.5.1 Supported DMA Paths 157
9.5.2 DMA Timing 157
9.5.3 Scatter-Gather 157
9.6 X-Bus 158
9.7 Keyboard/Mouse Controller 159
9.7.1 Keyboard/Mouse Control Registers 159
9.8 Real Time Clock (RTC) 160
9.8.1 RTC Address and NMI Enable Register 160
9.8.2 RTC Data Register 160
9.9 Non-Volatile RAM (NVRAM) 161
9.9.1 NVRAM Address Register Low 161
9.9.2 NVRAM Address Register High 161
9.9.3 NVRAM Data Register 161
9.10 Motherboard Presence Detect Registers 162
9.10.1 Floppy Media Sense ID 162
9.10.2 Equipment Presence Register 163
9.10.3 L2 ID Register 164
9.10.4 Motherboard ID Register 165
9.10.5 CPU ID Registers 166
9.10.6 DRAM ID Registers 167
Section 10 System EPLD 169
10.1 External Registers 169
10.2 Internal Registers 170
10.2.1 Storage Light Register 171
10.2.2 System Control Register 081C 172
10.2.3 Power Management Control Registers 174
10.2.4 Power Management Control Register 1 174
10.2.5 Power Management Control Register 2 174
10.2.6 IRQ13 Interrupt Request Active Register (Not Supported) 175
10.2.7 Freeze Clock Registers 176
10.2.7.1 Freeze Clock Register (FCR) Low 176
10.2.7.2 Freeze Clock Register (FCR) High 177
10.2.8 Serial ROM Control Register 178
10.2.8.1 Serial ROM Communications Protocol 179
10.2.8.2 Serial ROM vs. PD bits 179
10.2.9 L2 Control Register 180
10.2.10 CPU Sequence Register 180
10.2.11 CPU Enable Register 181
10.2.11.1 External Hardware Reset 181
10.3 Signal Descriptions 182
10.4 EPLD Design Equations 187
10.5 EPLD Pinout 202
Section 11 I/O Subsystems 205
11.1 Ethernet Subsystem 205
11.1.1 Ethernet Physical and Electrical Design Guidelines 205
11.1.1.1 Ethernet Power and Ground Guidelines 206
11.1.1.2 Ethernet 10BASE-T Layout Guidelines 206
11.1.1.3 Ethernet Oscillator Guidelines 206
11.1.2 Ethernet Sleep Mode 206
11.2 SCSI Subsystem 207
11.2.1 SCSI Physical and Electrical Design Guidelines 207
11.2.1.1 SCSI Component Location 207
11.2.1.2 SCSI Bus Routing 207
11.2.1.3 SCSI Decoupling 207
11.2.1.4 SCSI Impedance Matching 207
11.2.1.5 SCSI EMC Considerations 207
11.2.2 SCSI Termination 208
11.2.3 Cable/Device Presence Detect 209
11.2.4 SCSI Interrupts 209
11.3 Native I/O Subsystems 210
11.4 Business Audio Subsystem 210
11.4.1 Audio Performance 212
11.4.2 Audio Connector Specifications 213
11.4.3 Audio Control Registers 214
11.4.3.1 Audio Index Register 214
11.4.3.2 Audio Indexed Data Register 214
11.4.4 Audio Status Register 215
11.4.5 Audio PIO Data Register 216
11.4.6 The CS4232 Logical Device 217
11.4.7 Control Register 0 217
11.4.8 Control Register 1 218
11.4.9 Joystick Port 218
11.4.10 SoundBlaster Registers 219
11.4.11 MPU-401 MIDI 221
11.4.11.1 MIDI Status Register 221
Section 12 System Firmware 223
12.1 Introduction 223
12.2 Power On System Test 223
12.3 Boot Record Format 223
12.3.1 Boot Record 223
12.3.1.1 PC Partition Table Entry 224
12.3.1.2 Extended DOS Partition 225
12.3.1.3 PowerPC Reference Platform Partition Table Entry 226
12.3.2 Loading the Load Image 227
12.4 System Configuration 229
12.4.1 System Console 229
12.4.2 System Initialization 229
12.4.3 Main Menu 230
12.4.3.1 System Configuration Menu 231
12.4.3.2 Run a Program 237
12.4.3.3 Reprogram Flash Memory 238
12.4.3.4 Exit Options 239
12.4.4 Default Configuration Values 239
Section 13 Registers and System Setup 241
13.1 CPU Initialization 241
13.1.1 Fast L2/Data Streaming Mode (No-DRTRY#) 241
13.2 660 Bridge Initialization 242
13.2.1 CPU to PCI Configuration Transactions 242
13.2.1.1 Preferred Method of Generating PCI Configuration Transactions 242
13.2.1.2 650 Bridge Compatible Method 243
13.2.2 PCI Configuration Scan 243
13.2.2.1 Multi-Function Adaptors 243
13.2.2.2 PCI to PCI Bridges 243
13.2.3 660 Bridge Indexed BCR Summary 243
13.3 ISA Bridge (SIO) Initialization 247
13.3.1 ISA Bridge PCI Configuration Registers 250
13.4 MPIC Initialization 251
13.4.1 MPIC PCI Configuration Registers 251
13.4.2 MPIC PCI I/O Registers 251
13.4.2.1 MPIC Global Registers (PCI I/O) 251
13.4.2.2 MPIC Interrupt Source Configuration Registers (PCI I/O) 253
13.4.2.3 MPIC Per Processor Registers (PCI I/O) 254
13.5 Ethernet Initialization 255
13.5.1 Ethernet PCI Configuration Registers 255
13.5.2 Ethernet PCI I/O Registers 256
13.5.3 Ethernet CSR and BSR Registers 257
13.5.4 Ethernet EEPROM Interface 258
13.6 SCSI Initialization 260
13.6.1 SCSI PCI Configuration Registers 260
13.6.2 SCSI PCI I/O Registers 260
13.7 SuperI/O Initialization 263
13.7.1 SuperI/O Pin Strap Configuration 263
13.7.2 SuperI/O Configuration Register Configuration 263
13.7.3 SuperI/O Controller Register Access 264
13.7.3.1 SuperI/O FDC Registers 264
13.7.3.2 SuperI/O UART Registers 264
13.7.3.3 SuperI/O Parallel Port Registers 264
13.7.3.4 SuperI/O IDE Registers 265
13.8 Business Audio Initialization 265
13.8.1 CS4232 Initialization 265
13.8.1.1 Config State 265
13.8.1.2 Device 266
13.8.1.3 ADDRESS0, ADDRESS1, ADDRESS2 267
13.8.1.4 INT0, INT1 267
13.8.1.5 DMA0, DMA1 267
13.8.1.6 ACTIVATE 268
13.8.1.7 WAIT_FOR_KEY 268
13.9 Reference Design Combined Register Listing 268
13.9.1 ISA Registers 268
13.9.1.1 Direct Access ISA Registers 268
Section 14 Riser 277
14.1 Dual Bus Riser Connector Features 277
14.2 Special Comments about Riser and Motherboard Wiring 278
14.3 3.3v, 6-Pin Connector for PCI Slots 278
14.4 Current Capacity of Connectors on the Riser 279
14.5 Riser Connector 279
14.6 PCI Connector (On Riser) 282
14.7 3.3v, 6-Pin Connector (On Riser) 284
14.8 ISA Connector (On Riser) 284
Section 15 Power 287
15.1 External Power Supply Requirements 287
15.1.1 Power Supply Current Requirements 288
15.1.2 Power Supply Power Requirements 289
15.1.3 Additional Power Supply Requirements 290
15.2 Onboard 3.6v Regulator 290
Section 16 Mechanical 291
16.1 System Layout Drawings 292
16.1.1 System Layout 292
16.1.2 System 3D Sheet 1 293
16.1.3 System 3D Sheet 2 294
16.1.4 System Layout - Rear Panel Connector Locations 295
16.2 Motherboard 296
16.2.1 Motherboard Component Locator 296
16.2.2 Motherboard Mounting Holes 297
16.2.3 Motherboard Header and Jumper Locations 298
16.2.4 Motherboard Connector Locations 299
16.2.5 Motherboard Connector Details - Sheet 1 of 2 300
16.2.6 Motherboard Connector Details - Sheet 2 of 2 301
16.3 CPU Card 302
16.3.1 CPU Card 3D Views 302
16.3.2 CPU Card Layout 303
16.3.3 CPU Card Fansink Assembly 304
16.4 Riser 305
16.4.1 Riser Mechanical 305
16.4.2 Riser Details 306
16.5 L2 Card 307
16.5.1 Motherboard L2 Card Connector for 5v Tolerant Systems 307
16.5.2 Outline Drawing of 5v Output L2 Card 307
16.5.3 Motherboard L2 Card Connector for 3.3v Only Systems 308
16.5.4 Outline Drawing of 3.3v Output L2 Card 308
Section 17 Connectors 309
17.1 Connector Locations 310
17.2 Connectors 311
17.2.1 Battery Connector BATTERY 311
17.2.2 DRAM SIMM Connectors J0, J1, J2, J3, J4, J5, J6, J7 311
17.2.3 Mouse Connector J10 312
17.2.4 Keyboard Connector J11 312
17.2.5 Power Connector J13 313
17.2.6 Riser Connector J14 314
17.2.7 External SCSI Device Connector J19 318
17.2.8 Ethernet 10BASE-T Connector J21 319
17.2.9 CD-ROM Connector J22 319
17.2.10 Momentary On-Off Power Switch Connector J23 (Not Used) 319
17.2.11 Parallel Connector J25 320
17.2.12 Serial Port 1 (External) Connector J26 321
17.2.13 Serial Port 2 (Internal) Connector J27 321
17.2.14 Power Up Configuration Jumper J28 321
17.2.15 AUX5/ON-OFF Connector J29 322
17.2.16 Speaker Connector J31 and J39 322
17.2.17 Internal SCSI Device Connector J32 323
17.2.18 Game Port Connector J33 324
17.2.19 Fansink Connectors J34, J36, J43, J45 324
17.2.20 Box Fan Connector J37 324
17.2.21 Reset Switch Connector J38 325
17.2.22 Line In Jack J40 325
17.2.23 Power Good LED Connector J41 325
17.2.24 Floppy Diskette Drive (FDD) Connector J42 326
17.2.25 HDD LED Connector J44 326
17.2.26 Microphone Jack J46 326
17.2.27 Line Out Jack J47 327
17.2.28 Headphone Jack J48 327
17.2.29 Internal/FaxModem Connector J49 327
17.2.30 Riser 3.3v Power Connector J50 328
17.2.31 Riser 3.3v Power Cable 328
17.2.32 3.3v Power Connector J51 328
Section 18 Physical Design Guidelines 329
18.1 Motherboard Construction 329
18.2 Riser Construction 331
18.3 Cheetah3 Board Construction 333
18.4 General Wiring Guidelines 335
18.5 Clock Wires 336
18.6 Noise Sensitive Wires 338
18.6.1 To Be Run With Adjacent Grounds 338
18.6.2 To Be Run With No Wires in Adjacent Channels 339
18.7 CEC Critical Wires 340
18.8 L2 Cache Critical Wires 341
18.9 PCI Critical Control Wires 341
18.10 PCI Address/Data Wires 341
18.11 SCSI I/O Wires 342
18.12 Audio I/O Wires 342
18.13 Input/Output Wires 343
18.14 Ethernet Wires 344
18.15 Memory Wires 345
18.16 Battery Wires 345
18.17 Fan Wires 345
18.18 8mm Tape Contents and Extract Instructions 346
18.18.1 Download Instructions 346
18.18.2 Cadence Version 346
18.18.3 Tape Contents 346
Section 19 Bills of Materials 347
19.1 Motherboard Bill of Materials 347
19.2 CPU Card Bills of Materials 360
19.3 Riser Bill of Materials 366
Section 20 Errata 367
Section 21 Schematics
Motherboard Schematics
CPU Schematics
Riser Schematics
Section 22 Data Sheets
MPIC
DRAM
SRAM
Figure 1. Reference Design Block Diagram ( 60x and PCI Bus ) 25
Figure 2. Reference Design Block Diagram ( ISA and XBUS ) 26
Figure 3. CPU Bus Block Diagram 33
Figure 4. Contiguous PCI I/O Address Translation 37
Figure 5. Non-Contiguous PCI I/O Address Transformation 38
Figure 6. Non-Contiguous PCI I/O Address Translation 39
Figure 7. CPU Card Physical Envelope 57
Figure 8. CPU Slot Card Connector (Socket) 58
Figure 9. Auxiliary CPU Slot Connector 63
Figure 10. Read Cycle On the Bus 66
Figure 11. L2 Tag/SRAM Card Airflow and Keying 73
Figure 12. L2 Slot Card Connector (Socket) 74
Figure 13. JTAG/RISCWatch Connector and Configuration Jumpers 78
Figure 14. Data and Data Parity Path 79
Figure 15. Address Path 79
Figure 16. Control Path (TA#,TS#, AACK#, ARTRY#, TT[0:3]) 79
Figure 17. DBB# Path 79
Figure 18. Model of CPU Card to Motherboard Interface (CPU Slot) 80
Figure 19. Model of L2 Card to Motherboard Interface (L2 Slot) 80
Figure 20. Address Path 81
Figure 21. Endian Mode Block Diagram 85
Figure 22. Example at Address xxxx xxx0 88
Figure 23. Example at Address xxxx xxx2 89
Figure 24. Double Byte Write Data ab at Address xxxx xxx0 92
Figure 25. Word (4-Byte) Write of 0a0b0c0dh at Address xxxx xxx4 94
Figure 26. Instruction Alignment Example 97
Figure 27. Wrong Instruction Read When Unmunger is used 98
Figure 28. Instruction Stream to Switch Endian Modes 99
Figure 29. CPU Card Block Diagram 101
Figure 30. J2 Auxiliary Test Connector 102
Figure 31. CPU Card Fansink Assembly 103
Figure 32. Fansink With Power Cable 103
Figure 33. Signal Group Electrical Model 107
Figure 34. J1 Outline 108
Figure 35. DRAM Banks 0 and 1 Organization 114
Figure 36. DRAM Banks 2 and 3 Organization 115
Figure 37. Interrupt Subsystem 118
Figure 38. PCI Expansion Slot Interrupt Connections 119
Figure 39. HRESET# Signal Circuit 123
Figure 40. SRESET# Signal Circuit 125
Figure 41. SMP System Reset 128
Figure 42. System Clocks 138
Figure 43. Frequency Selection Block Diagram 139
Figure 44. Typical X-Bus Registers 158
Figure 45. Typical X-Bus Registers 162
Figure 46. DRAM PD Registers 167
Figure 47. Typical External Register 169
Figure 48. Read Cycle On the Bus 179
Figure 49. General SCSI Bus Wiring 208
Figure 50. Audio Flow Diagram 211
Figure 51. Boot Record 224
Figure 52. Partition Table Entry 224
Figure 53. Partition Table Entry Format for an Extended Partition 226
Figure 54. Partition Table Entry for PowerPC Reference Platform 226
Figure 55. PowerPC Reference Platform Partition 227
Figure 56. System Initialization Screen 229
Figure 57. Configuration Utility Main Menu 230
Figure 58. System Configuration Menu 231
Figure 59. System Information Screen 232
Figure 60. Device Configuration Screen 233
Figure 61. SCSI Devices Screen 234
Figure 62. Boot Devices Screen 235
Figure 63. Set Date and Time Screen 236
Figure 64. Run a Program Screen 237
Figure 65. Reprogram the Flash Memory Screen 238
Figure 66. Dual Bus Riser Connector 277
Figure 67. Riser Connector 279
Figure 68. PCI Connector 282
Figure 69. 3.3v, 6-Pin Connector 284
Figure 70. ISA Connector 284
Figure 71. Riser Power Cable 328
Figure 72. Motherboard Signal and Power Layers 329
Figure 73. Typical Motherboard Wiring Channel Top View 329
Figure 74. Motherboard Fabrication 330
Figure 75. Riser Signal and Power Layers 331
Figure 76. Typical Riser Wiring Channel Top View 331
Figure 77. Riser Fabrication 332
Figure 78. Signal and Power Layers 333
Figure 79. Typical Cheetah3 Wiring Channel Top View 333
Figure 80. Cheetah3 Board Fabrication 334
Figure 81. Power Plane Split 335
Table 1. Quickstart Peripheral List 31
Table 2. TT[0:3] (Transfer Type) Decoding by 660 Bridge 35
Table 3. 660 Bridge Address Mapping of CPU Bus Transactions 36
Table 4. CPU Slot Signal Descriptions 44
Table 5. CPU Slot DC Characteristics 56
Table 6. CPU Slot AC Timing (5) 56
Table 7. CPU Slot Power Supplies (2) 57
Table 8. Main CPU Slot Connector Pin Assignments 59
Table 9. Aux CPU Slot Connector Pinout 63
Table 10. L2 Cache ID ROM 65
Table 11. Serial Communications Protocol Sequence 66
Table 12. L2 Slot Signal Descriptions 67
Table 13. L2 Slot DC Characteristics (2) 71
Table 14. L2 Slot AC Timing (5) 72
Table 15. L2 Slot Power Supplies (2) 72
Table 16. L2 Slot Pinout 75
Table 17. J18 Pin Assignments 78
Table 18. Endian Mode Operations 83
Table 19. 604 LE Mode Address Transform 84
Table 20. 660 Bridge Endian Mode Byte Lane Steering 85
Table 21. 660 Bit Transfer 86
Table 22. Memory in BE Mode 89
Table 23. Memory in LE Mode 90
Table 24. PCI in BE Mode 90
Table 25. PCI in LE Mode 91
Table 26. Two Byte Transfer Information 93
Table 27. Rearranged 2-Byte Transfer Information 93
Table 28. 4-Byte Transfer Information 95
Table 29. Rearranged 4-Byte Transfer Information 96
Table 30. J2 Aux Connector Pinout 102
Table 31. Voltage Ratings 105
Table 32. DC Recommended Operating Conditions 105
Table 33. Thermal Recommended Operating Conditions 106
Table 34. AC Timing Recommended Operating Conditions 106
Table 35. CPU Card Pin List 108
Table 36. Supported DRAM Modules 113
Table 37. MPIC Interrupts 119
Table 38. ISA Interrupt Assignments 120
Table 39. CPU Slot PD Bit Encoding 140
Table 40. CPU Clock Control Logic 141
Table 41. Supported DRAM Modules 144
Table 42. Reference Design Responses to PCI_C[3:0] Bus Commands 146
Table 43. Mapping of PCI Memory Space, Part 1 147
Table 44. Mapping of PCI Memory Space, Part 2 147
Table 45. Mapping of PCI Master I/O Transactions 148
Table 46. Active CAS# Lines - PCI to Memory Writes, BE or LE Mode 150
Table 47. 660 Bridge Address Mapping of CPU Bus Transactions 151
Table 48. DMA Assignments 156
Table 49. L2 Cache SRAM/TagRAM PD Table 164
Table 50. Motherboard ID Encoding 165
Table 52. DRAM PD Registers 167
Table 53. SIMM Definition 167
Table 54. External Register Support 170
Table 55. Internal Register Support 170
Table 56. External Register Support 172
Table 57. Signal Descriptions 182
Table 58. EPLD Pinout 202
Table 59. Business Audio Subsystem Performance 212
Table 60. Business Audio Connector Specifications 213
Table 61. SoundBlaster Addresses 219
Table 62. IDSEL Assignments 242
Table 63. 660 Bridge Indexed BCR Listing 244
Table 64. Summary of SIO Register Setup
(Configuration Address = 8080 08xx) 248
Table 65. Summary of SIO PCI Configuration Registers 250
Table 66. MPIC PCI Configuration Registers 251
Table 67. MPIC Global Registers (PCI I/O) 251
Table 68. MPIC Interrupt Source Configuration Registers (PCI I/O) 253
Table 69. MPIC Per Processor Registers (PCI I/O) 254
Table 70. Ethernet PCI Configuration Registers 255
Table 71. Ethernet I/O Map In Word I/O Mode (DWIO = 0) 256
Table 72. Ethernet I/O Map In DWord I/O Mode (DWIO = 1) 256
Table 73. Ethernet CSR Registers 257
Table 74. Ethernet BCR Registers 258
Table 75. Ethernet EEPROM Content 258
Table 76. SCSI PCI Configuration Registers 260
Table 77. SCSI PCI I/O Registers 261
Table 78. SuperI/O BADDR Encoding 263
Table 79. SuperI/O Configuration Registers (ISA Bus Indirect Access) 263
Table 80. SuperI/O FDC Registers (ISA I/O) 264
Table 81. SuperI/O UART Registers (One Set Per UART) (ISA I/O) 264
Table 82. SuperI/O Parallel Port Registers (ISA I/O) 264
Table 83. SuperI/O IDE Registers (ISA I/O) 265
Table 84. Settings for DMA Channels 266
Table 85. Settings for Interrupt Channels 266
Table 86. Device Configuration Commands 266
Table 87. CS4232 Logical Devices 267
Table 88. Logical Device Resources 267
Table 89. Base Address Commands 267
Table 90. DMA Channels 267
Table 91. Activate Commands 268
Table 92. Combined Direct Access ISA Bus I/O Register Listing 268
Table 93. Connector Capacity 279
Table 94. Riser Connector Pin Assignments 279
Table 95. PCI Connector Pin Assignments 282
Table 96. 3.3v, 6-Pin Connector Pin Assignments 284
Table 97. ISA Connector Pin Assignments 284
Table 98. External Power Supply Requirements 287
Table 99. Approximate Current Capacities and Requirements (Amps) 288
Table 100. Approximate Power Capacities and Requirements (Watts) 289
Table 101. Specifications for 3.6v Regulator on the Motherboard 290
Table 102. J14 Riser Connector Pin Assignments 314
Table 103. Order of Importance for Meeting Design Rules 335
Table 104. Clock Wires 336
Table 105. Noise Sensitive Wires (Ground Wires Adjacent) 338
Table 106. Noise Sensitive Wires (No Wires Adjacent) 339
Table 107. CEC Critical Wires 340
Table 108. L2 Critical Control Wires 341
Table 109. PCI Critical Control Wires 341
Table 110. PCI Address/Data Wires 341
Table 111. SCSI I/O Wires 342
Table 112. Audio I/O Wires 342
Table 113. I/O Wires 343
Table 114. TPI Wires 344
Table 115. Memory Wires 345
The MPIC chip referenced in this document is not currently generally available from IBM. The Verilog source of MPIC is available from IBM under license at no charge. Contact your IBM representative for details.
Audience:
This reference design is designed for engineers and system designers who are interested in implementing PowerPC systems that are compliant with the PowerPC Reference Platform Specification. The material requires a detailed understanding of computer systems at the hardware and software level.
Reference Material:
Understanding of the relevant areas of the following documents is required for a good understanding of the reference design:
Kilobytes, megabytes, and gigabytes are indicated by a single capital letter after the numeric value. For example, 4K means 4 kilobytes, 8M means 8 megabytes, and 4G means 4 gigabytes.
The terms DIMM and SIMM are often used to mean DRAM module.
Hexadecimal values are identified (where not clear from context) with a lower-case letter h at the end of the value. Binary values are identified (where not clear from context) with a lower-case letter b at the end of the value.
In identifying ranges of values from and to are used whenever possible. The range statement from 0 to 2M means from and including zero up to (but not including) two megabytes. The hexadecimal value for the range from 0 to 64K is: 0000h to FFFFh.
The terms asserted and negated are used extensively. The term asserted indicates that a signal is active (logically true), regardless of whether that level is represented by a high or low voltage. The term negated means that a signal is not asserted. The # symbol at the end of a signal name indicates that the active state of the signal occurs with a low voltage level.
Signal ranges are given from MSb (most significant bit) to LSb in the form SIGNAL[MSb:LSb]. For example, CPU_ADDR[0:23] refers to CPU_ADDR signals 0 thru 23, where 0 is the most significant. Note that this convention allows easy identification of the endian mode of the nomenclature. DATA[0:12] is labeled in big endian fashion, and DATA[12:0] is referred to in little endian order.
