// Fri May 03 13:35:20 1996
// C:\PDS\SRAM_DMA\SRAM_DMA.LDF generated using Lattice pDS Version 3.0.39A-QA

LDF 1.00.00 DESIGNLDF;
DESIGN DMA_SM_;
AUTHOR Brian Nu;
DESCRIPTION
This design will provide a 512X18 SRAM and 4 X DMA channels and DMA arbitrition state machine. ;

PART ispLSI6192SM-70LM208;

OPTION PULLUP ON;

OPTION MINIMIZE STRONGMIN;

DECLARE

END;  //DECLARE

MODULE_DEF

MODULE MEMORY MEMORY;
    CONFIG;
	SINGLEB 256 18 BW;
    END;
    PORT;
	DINB[0..17] [DIN0..DIN17];
	DOUTB[0..17] [RDOUT0..RDOUT17] ;
	ADDRB[0..7] [A1..A8];
	RWHB RWH_ ;
	RWLB RWL_ ;
	CSB SRAM_ ;
    END;
END; 

MODULE REGISTER M1;
// FOUR COUNTERS UP/DN, 8/16 BITS, PARALLEL LOAD & 4 BANK REGISTER FILE
    CONFIG;
	BANK0 RF CLK SYSCLK ;
	BANK1 COUNTER CLK SYSCLK UP 16;
	BANK2 RF CLK SYSCLK ;
	BANK3 COUNTER CLK SYSCLK UP 16;
	BANK4 RF CLK SYSCLK ;
	BANK5 COUNTER CLK SYSCLK UP 16;
	BANK6 RF CLK SYSCLK ;
	BANK7 COUNTER CLK SYSCLK UP 16;
    END;
    PORT;
	DIN[0..15] [DIN0 .. DIN15] ;
	DOUT[0..15] [RCD0 .. RCD15] ;
	SEL[0..2] [RC_SEL0 .. RC_SEL2] ;
	EN RW_ ;
	CICH[1,3,5,7] S2, S4, S6, S8;
	COUT[1,3,5,7] TC1 , TC2 , TC3 , TC4 ;
    END;
END; 
END;  //MODULE_DEF

SYM GLB  C0a  1  CNTR3;
//CDU38 ([Q0..Q7],CAO,[D0..D7],CAI,CLK,LD,EN,CD);
CDU38 ([CNTR3_0..CNTR3_7],CNTR3L_CAO,[RCD0..RCD7],VCC,SYSCLK,S5,S6,GND);
END;

SYM GLB  C1a  1  CNTR4;
//CDU38 ([Q0..Q7],CAO,[D0..D7],CAI,CLK,LD,EN,CD);
CDU38 ([CNTR4_0..CNTR4_7],CNTR4L_CAO,[RCD0..RCD7],VCC,SYSCLK,S7,S8,GND);
END;

SYM GLB  C0b  1  ;
CDU38 ([CNTR3_8..CNTR3_15],CNTR3H_CAO,[RCD8..RCD15],CNTR3L_CAO,SYSCLK,S5,S6,GND);
END;

SYM GLB  C1b  1  ;
CDU38 ([CNTR4_8..CNTR4_15],CNTR4H_CAO,[RCD8..RCD15],CNTR4L_CAO,SYSCLK,S7,S8,GND);
END;

SYM GLB  E0a  1  ;
// XOR8 (Z0,[A0..A7]);
 XOR8 (PARITY_16,[RDOUT0..RDOUT7]);
END;

SYM GLB  E0b  1  ;
// XOR8 (Z0,[A0..A7]);
 XOR8 (PARITY_17,[RDOUT8..RDOUT15]);
END;

SYM GLB  E1a  1  ;
SIGTYPE R6192 OE;
EQUATIONS
R6192 = RW_ & SEL6192;
RWH_ = !(!RW_ & A0);
RWL_ = !(!RW_ & !A0);
END;
END;

SYM GLB  E1b  1  ;
EQUATIONS
SEL6192 = !SRAM_ # !DMASEL_;
RC_SEL0 = (!DMASEL_ & A0) # CNTSEL0;
RC_SEL1 = (!DMASEL_ & A1) # CNTSEL1;
RC_SEL2 = (!DMASEL_ & A2) # CNTSEL2;
END;
END;

SYM GLB  E2a  1  PARITY;
// XOR8 (Z0,[A0..A7]);
 XOR8 (DIN16,[DIN0..DIN7]);
END;

SYM GLB  E2b  1  ;
// XOR8 (Z0,[A0..A7]);
 XOR8 (DIN17,[DIN8..DIN15]);
END;

SYM GLB  B0a  1  ADMUX;
 //MUX44 (Z0,Z1,Z2,Z3,[A0..A3],[B0..B3],[C0..C3],[D0..D3],S0,S1);
MUX44 (CA0,CA1,CA2,CA3,[CNTR1_0..CNTR1_3],[CNTR2_0..CNTR2_3],[CNTR3_0..CNTR3_3],[CNTR4_0..CNTR4_3],CAS0,CAS1);
END;

SYM GLB  E3b  1  MAXH;
// MUX82 (Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7,[A0..A7],[B0..B7],S0);
MUX82 (DOUT8,DOUT9,DOUT10,DOUT11,DOUT12,DOUT13,DOUT14,DOUT15,[RDOUT8..RDOUT15],[CA8..CA15],SRAM_);
END;

SYM GLB  F0a  1  MUXL2;
// MUX82 (Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7,[A0..A7],[B0..B7],S0);
MUX82 (DOUT0,DOUT1,DOUT2,DOUT3,DOUT4,DOUT5,DOUT6,DOUT7,[RDOUT0..RDOUT7],[CA0..CA7],SRAM_);
END;

SYM GLB  F0b  1  IDLE;
EQUATIONS
IDLE = !S1 & !S2 & !S3 & !S4 & !S5 & !S6 & !S7 & !S8;
END;
END;

SYM GLB  F1a  1  S1-S4;
SIGTYPE S1 REG OUT;
SIGTYPE S2 REG OUT;
SIGTYPE S3 REG OUT;
SIGTYPE S4 REG OUT;
EQUATIONS
S1.CLK = SYSCLK;
S2.CLK = SYSCLK;
S3.CLK = SYSCLK;
S4.CLK = SYSCLK;
S1 = REQ1 & IDLE;
S2 = S1 # (S2 & !TC1);
S3 = REQ2 & IDLE & !REQ1;
S4 = S3 # (S4 & !TC2);
END;
END;

SYM GLB  F1b  1  ;
SIGTYPE S5 REG OUT;
SIGTYPE S6 REG OUT;
SIGTYPE S7 REG OUT;
SIGTYPE S8 REG OUT;
EQUATIONS
S5.CLK = SYSCLK;
S6.CLK = SYSCLK;
S7.CLK = SYSCLK;
S8.CLK = SYSCLK;
S5 = REQ3 & IDLE & !REQ1 & !REQ2;
S6 = S5 # (S6 & !TC3);
S7 = REQ4 & IDLE & !REQ1 & !REQ2 & !REQ3;
S8 = S7 # (S8 & !TC4);
END;
END;

SYM GLB  F2a  1  ;
SIGTYPE PARITY_ERR REG OUT;
EQUATIONS
PARITY_ERR = (RW_ & (PARITY_16 $ RDOUT16)) # (RW_ & (PARITY_17 $ RDOUT17));
PARITY_ERR.CLK = SYSCLK;
END;
END;

SYM GLB  F2b  1  ;
EQUATIONS
CNTSEL0 = !S1 # !S2 # !S3 # !S4 # !S5 # !S6 # !S7 # !S8;
CNTSEL1 = S3 # S4 # S7 # S8;
CNTSEL2 = S5 # S6 # S7 # S8;
END;
END;

SYM GLB  A2b  1  ;
CDU38 ([CNTR1_8..CNTR1_15],CNTR1H_CAO,[RCD8..RCD15],CNTR1L_CAO,SYSCLK,S1,S2,GND);
END;

SYM GLB  B0b  1  ;
MUX44 (CA4,CA5,CA6,CA7,[CNTR1_4..CNTR1_7],[CNTR2_4..CNTR2_7],[CNTR3_4..CNTR3_7],[CNTR4_4..CNTR4_7],CAS0,CAS1);
END;

SYM GLB  B1a  1  ;
MUX44 (CA8,CA9,CA10,CA11,[CNTR1_8..CNTR1_11],[CNTR2_8..CNTR2_11],[CNTR3_8..CNTR3_11],[CNTR4_8..CNTR4_11],CAS0,CAS1);
END;

SYM GLB  B1b  1  ;
MUX44 (CA12,CA13,CA14,CA15,[CNTR1_12..CNTR1_15],[CNTR2_12..CNTR2_15],[CNTR3_12..CNTR3_15],[CNTR4_12..CNTR4_15],CAS0,CAS1);
END;

SYM GLB  A1a  1  CNTR1;
//CDU38 ([Q0..Q7],CAO,[D0..D7],CAI,CLK,LD,EN,CD);
CDU38 ([CNTR1_0..CNTR1_7],CNTR1L_CAO,[RCD0..RCD7],VCC,SYSCLK,S1,S2,GND);
END;

SYM GLB  A2a  1  CNTR2;
//CDU38 ([Q0..Q7],CAO,[D0..D7],CAI,CLK,LD,EN,CD);
CDU38 ([CNTR2_0..CNTR2_7],CNTR2L_CAO,[RCD0..RCD7],VCC,SYSCLK,S3,S4,GND);
END;

SYM GLB  A3a  1  ;
CDU38 ([CNTR2_8..CNTR2_15],CNTR2H_CAO,[RCD8..RCD15],CNTR2L_CAO,SYSCLK,S3,S4,GND);
END;

SYM GLB  A3b  1  ;
EQUATIONS
CAS1 = S5 # S6 # S7 # S8;
CAS0 = S3 # S4 # S7 # S8;
END;
END;

// No ldf text found for cell: B2a

// No ldf text found for cell: B2b

// No ldf text found for cell: B3a

// No ldf text found for cell: B3b

// No ldf text found for cell: A1b

// No ldf text found for cell: C2a

// No ldf text found for cell: C3a

// No ldf text found for cell: D0a

// No ldf text found for cell: D1a

// No ldf text found for cell: D2a

// No ldf text found for cell: D2b

// No ldf text found for cell: D3a

// No ldf text found for cell: F3b

// No ldf text found for cell: F3a

// No ldf text found for cell: A0b

// No ldf text found for cell: C2b

// No ldf text found for cell: C3b

// No ldf text found for cell: D0b

// No ldf text found for cell: D1b

// No ldf text found for cell: D3b

// No ldf text found for cell: A0a

// No ldf text found for cell: E3a

SYM IOC  IO25  1  D6;
//BI11 (Z0,XB0,A0,OE);
 BI11 (DIN6,XD6,DOUT6,R6192);
END;

SYM IOC  IO26  1  D5;
//BI11 (Z0,XB0,A0,OE);
 BI11 (DIN5,XD5,DOUT5,R6192);
END;

SYM IOC  IO27  1  D4;
//BI11 (Z0,XB0,A0,OE);
 BI11 (DIN4,XD4,DOUT4,R6192);
END;

SYM IOC  IO28  1  D3;
//BI11 (Z0,XB0,A0,OE);
 BI11 (DIN3,XD3,DOUT3,R6192);
END;

SYM IOC  IO29  1  D2;
//BI11 (Z0,XB0,A0,OE);
 BI11 (DIN2,XD2,DOUT2,R6192);
END;

SYM IOC  Y0  1  CLK;
//IB11 (Z0,XI0);
IB11 (SYSCLK,XSYSCLK);
END;

SYM IOC  IO15  1  A0;
//IB11 (Z0,XI0);
IB11 (A0,XA0);
END;

SYM IOC  IO14  1  A1;
//IB11 (Z0,XI0);
IB11 (A1,XA1);
END;

SYM IOC  IO13  1  A2;
//IB11 (Z0,XI0);
IB11 (A2,XA2);
END;

SYM IOC  IO0  1  DMASEL_;
//IB11 (Z0,XI0);
IB11 (DMASEL_,XDMASEL_);
END;

SYM IOC  IO1  1  SRAM_;
//IB11 (Z0,XI0);
IB11 (SRAM_,XSRAM_);
END;

SYM IOC  IO2  1  RW_;
//IB11 (Z0,XI0);
IB11 (RW_,XRW_);
END;

SYM IOC  IO32  1  REQ3;
//IB11 (Z0,XI0);
IB11 (REQ3,XREQ3);
END;

SYM IOC  IO33  1  REQ2;
//IB11 (Z0,XI0);
IB11 (REQ2,XREQ2);
END;

SYM IOC  IO34  1  REQ1;
//IB11 (Z0,XI0);
IB11 (REQ1,XREQ1);
END;

SYM IOC  IO35  1  REQ0;
//IB11 (Z0,XI0);
IB11 (REQ4,XREQ4);
END;

SYM IOC  IO36  1  GRNT3;
// OB11 (XO0,A0);
OB11 (XGRNT3,S6);
END;

SYM IOC  IO37  1  GRNT2;
// OB11 (XO0,A0);
OB11 (XGRNT2,S4);
END;

SYM IOC  IO38  1  GRNT1;
// OB11 (XO0,A0);
OB11 (XGRNT1,S2);
END;

SYM IOC  IO39  1  GRNT0;
// OB11 (XO0,A0);
OB11 (XGRNT4,S8);
END;

SYM IOC  IO12  1  A3;
//IB11 (Z0,XI0);
IB11 (A3,XA3);
END;

SYM IOC  IO11  1  A4;
//IB11 (Z0,XI0);
IB11 (A4,XA4);
END;

SYM IOC  IO10  1  A5;
//IB11 (Z0,XI0);
IB11 (A5,XA5);
END;

SYM IOC  IO9  1  A6;
//IB11 (Z0,XI0);
IB11 (A6,XA6);
END;

SYM IOC  IO8  1  A7;
//IB11 (Z0,XI0);
IB11 (A7,XA7);
END;

SYM IOC  IO7  1  A8;
//IB11 (Z0,XI0);
IB11 (A8,XA8);
END;

SYM IOC  IO6  1  A9;
//IB11 (Z0,XI0);
IB11 (A9,XA9);
END;

SYM IOC  IO5  1  A10;
//IB11 (Z0,XI0);
IB11 (A10,XA10);
END;

SYM IOC  IO31  1  ;
 //BI11 (Z0,XB0,A0,OE);
 BI11 (DIN0,XD0,DOUT0,R6192);
END;

SYM IOC  IO30  1  ;
//BI11 (Z0,XB0,A0,OE);
 BI11 (DIN1,XD1,DOUT1,R6192);
END;

SYM IOC  IO24  1  ;
//BI11 (Z0,XB0,A0,OE);
 BI11 (DIN7,XD7,DOUT7,R6192);
END;

SYM IOC  IO23  1  ;
//BI11 (Z0,XB0,A0,OE);
 BI11 (DIN8,XD8,DOUT8,R6192);
END;

SYM IOC  IO22  1  ;
//BI11 (Z0,XB0,A0,OE);
 BI11 (DIN9,XD9,DOUT9,R6192);
END;

SYM IOC  IO21  1  ;
//BI11 (Z0,XB0,A0,OE);
 BI11 (DIN10,XD10,DOUT10,R6192);
END;

SYM IOC  IO20  1  ;
//BI11 (Z0,XB0,A0,OE);
 BI11 (DIN11,XD11,DOUT11,R6192);
END;

SYM IOC  IO19  1  ;
//BI11 (Z0,XB0,A0,OE);
 BI11 (DIN12,XD12,DOUT12,R6192);
END;

SYM IOC  IO18  1  ;
//BI11 (Z0,XB0,A0,OE);
 BI11 (DIN13,XD13,DOUT13,R6192);
END;

SYM IOC  IO17  1  ;
//BI11 (Z0,XB0,A0,OE);
 BI11 (DIN14,XD14,DOUT14,R6192);
END;

SYM IOC  IO16  1  ;
//BI11 (Z0,XB0,A0,OE);
 BI11 (DIN15,XD15,DOUT15,R6192);
END;

SYM IOC  IO40  1  ;
 // OB11 (XO0,A0);
OB11 (XP_ERR,PARITY_ERR);
END;

SYM IOC  IO48  1  CA15;
 //OB11 (XO0,A0);
OB11 (XCA15,CA15);
END;

SYM IOC  IO49  1  CA14;
 //OB11 (XO0,A0);
OB11 (XCA14,CA14);
END;

SYM IOC  IO50  1  CA13;
 //OB11 (XO0,A0);
OB11 (XCA13,CA13);
END;

SYM IOC  IO51  1  CA12;
 //OB11 (XO0,A0);
OB11 (XCA12,CA12);
END;

SYM IOC  IO52  1  CA11;
 //OB11 (XO0,A0);
OB11 (XCA11,CA11);
END;

SYM IOC  IO53  1  CA10;
 //OB11 (XO0,A0);
OB11 (XCA10,CA10);
END;

SYM IOC  IO54  1  CA9;
 //OB11 (XO0,A0);
OB11 (XCA9,CA9);
END;

SYM IOC  IO55  1  CA8;
 //OB11 (XO0,A0);
OB11 (XCA8,CA8);
END;

SYM IOC  IO56  1  CA7;
 //OB11 (XO0,A0);
OB11 (XCA7,CA7);
END;

SYM IOC  IO57  1  CA6;
 //OB11 (XO0,A0);
OB11 (XCA6,CA6);
END;

SYM IOC  IO58  1  CA5;
 //OB11 (XO0,A0);
OB11 (XCA5,CA5);
END;

SYM IOC  IO59  1  CA4;
 //OB11 (XO0,A0);
OB11 (XCA4,CA4);
END;

SYM IOC  IO60  1  CA3;
 //OB11 (XO0,A0);
OB11 (XCA3,CA3);
END;

SYM IOC  IO61  1  CA2;
 //OB11 (XO0,A0);
OB11 (XCA2,CA2);
END;

SYM IOC  IO62  1  CA1;
 //OB11 (XO0,A0);
OB11 (XCA1,CA1);
END;

SYM IOC  IO63  1  CA0;
 //OB11 (XO0,A0);
OB11 (XCA0,CA0);
END;
END;  //LDF DESIGNLDF
