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*  RELEASE 0.12 BUGLIST                                                       *
*  Update - 10/29/90                                                          *
*  This file contains a list of bugs in the release 0.12 of the 320C50        *
*  simulator.                                                                 *
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SIMULATOR
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3135   V0.12   Fixed V0.20
Registers ST0,ST1,PMST,TREG1 & TREG2 are not saved on interrupt.

3224   V0.12   Fixed V0.20
Changing the data page pointer with the simulator DP command does not update
the reverse-assembler address.

3227   V0.12   Fixed V0.20
The following memory ranges in data space are not implemented as defined
by Spec 2.5:
             100-2ffh   data memory when CNF=0
             100-2ffh   reserved when CNF=1
             400-4ffh   data memory
             500-5ffh   reserved in data space

3228   V0.12   Fixed V0.20
The blocks of RAM B0 and B1 are 512 words of RAM, not 256.

3229   V0.12   Fixed V0.20
The on-chip single access RAM on the C50 in 9k words, not 8k words.

3230   V0.12   Fixed V0.20
The block repeat active flag (BRAF) is improperly cleared on a block repeat.
It is being cleared when the blockrepeat counter register (BRCR) decrements
to zero.  It should be cleared when the BRCR decrements below zero.  In
addition, the PMST register is improperly reset to zero at the completion of
a block repeat (only the BRAF should be cleared).

3231   V0.12   Fixed V0.20
The external interrupts are presently numbered INT0-INT2 instead of INT1-INT3
as they should be.

3234   V0.12   Fixed V0.20
Circular buffers should only work with an auxiliary register modification
other than zero.  The simulator allows an AR operation with no AR
modification to load CBSR into the current AR.  The value should only be
loaded if the current AR=CBER and a non-zero AR modification occurs.

3287   V0.12   Fixed V0.20
When bit 0 in PMST register is reset by executing a repeat block, all the
bits are reset to 0.  For example, enable the 3 T-REG and index register
option.  After a repeat block is finished everthing related to the PMST
register is reset.

3429   V0.12   Fixed V0.20
The RPTB instruction (repeat block) does not work unless it contains at least
3 instruction words.

3430   V0.12   Fixed V0.20
BCND BIO instructions branch when BIO = 1, but branch should occur when
BIO = 0.

3431   V0.12   Fixed V0.20
The SPLK instruction loops forever if used in a circular buffer in Single
in Single Access RAM.  For example:
        SLPK    #800,CBSR1
        SLPK    #800,CBSR1
        LAR      AR1,#800h
        SLPK    #(1<<3)+1,CBCR
        SLPK    #1,*+           ; Simulator gets stuck here.
        LAC      *+
        LAC      *+


3432   V0.12   Fixed V0.20
The BANZD instruction does not work.

3433   V0.12   Fixed V0.20
The RPT instruction does not work for values greater than 100 hex.

3434   V0.12   Fixed V0.20
MAR instruction generates  >>ERROR ACCESSED RESERVED MEMORY LOCATION
if the current auxillary register value is not a valid memory location.
But the MAR instruction does not access memory.

3435   V0.12   Fixed V0.20
Simulator does not load .data section.

3447   V0.12   Fixed V0.20
Conditional delayed branches (BCNDD) reset ARP=0 when the branch is taken
(that is, when the condition=true).

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