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*  RELEASE 0.21 BUGLIST                                                       *
*  Update - 2/5/91                                                            *
*  This file contains a list of bugs in the release 0.21 of the 320C50        *
*  simulator.                                                                 *
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SIMULATOR
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3505   V0.21   Fixed V0.30
After the repeat instructions have loaded registers BRCR and RPTC they
cannot be modified either from the CPU register window or by user's program
code.

3506   V0.21   Fixed V0.30
Clearing the PMST register BRAF bit (Block repeat active flag) has no effect
on the execution of the repeat block.

3507   V0.21   Fixed V0.30
The simulator allows repeat blocks of any length, but RPTB should not work
with blocks less than 3 words long.

3508   V0.21   Fixed V0.30
The BRCH register must be loaded at least 2 instructions prior to execution
of the RPTB instruction.  Also, RPT and RPTZ instructions using a direct
address repeat count must load the data memory location at two cycles
prior to the RPT instruction.  (Repeat instructions with immediate address
repeat count operate as expected).

3509   V0.21   Fixed V0.30
A repeat instruction, RPT, with a specified repeat value of 0 (repeat once)
does not operate correctly when a 2 word instruction is specified.
For example:
                RPT  #0
                BLDD #300,*+

3510   V0.21   Fixed V0.30
The delayed-call instruction cannot be used 2 words before the end of a
block repeat.  The simulator executes an infinite block repeat loop.
For example:
                LOOPHERE   RPTB  ENDLOOP-1
                           LACC  DAT1
                           CALLD TEST
                           ADD   DAT2
                           SACL  DAT1
                ENDLOOP

3511   V0.21   Fixed V0.30
Instructions referencing the PMST register are effected immediately by changes
to PMST when instead, they should not be effected until after a delay of 2
instuction cycles following the change.  That is, instructions should not be
effected if the PMST register is changed while the referencing instruction is
in the pipeline.

3512   V0.21   Fixed V0.30
The disassembler follows the C25 rather than the C5x mneumonic conventions in
some cases:
                                disassembles
                ADD   dma,16  ----------------> ADDH  dma
                AND   dsm,16  ----------------> ANDH  dma
                OR    dsm,16  ----------------> ORH   dma
                SUB   dsm,16  ----------------> SUBH  dma
                XOR   dsm,16  ----------------> XORH  dma
                LACC  dsm,16  ----------------> ZALH  dma
                LACL #k       ----------------> LAC   #k
                LST  #k, xxh  ----------------> LST2  xxh
                LST  #0, xxh  ----------------> LST1  xxh
                MAR  *,ARx    ----------------> LARP  ARx
                SST  #1, xxh  ----------------> SST1  xxh
                SST  #0, xxh  ----------------> SST2  xxh

3532   V0.21   Fixed V0.30
BANZ instruction does not work properly. Therefore c_int0 fails to initialize C
variables when using -c option.  example:
            .text
     MAIN   LDP     #0             ;ar0 = 0 initially
            MAR     *,AR0
            LAR     AR0,#60h
            LAR     AR0,*          ;ar0 <- (60h)
            BANZ    JP1,*-         ;Branch not take even when (60h!=0)
            NOP
            NOP
            NOP
            NOP
     SPIN   B       SPIN
            NOP
            NOP
     JP1    NOP
     SPIN2  B       SPIN2

Workaround:  Compile with -cr option, this works.

3549   V0.21   Fixed V0.30
The instructions OPL, APL, and XPL should clear the TC bit to 0 if the
result of the operation is 0.  Otherwise, the TC bit should be set to 1.
These instructions have no effect on the TC bit in the simulator Versions
0.12 and 0.21

3557   V0.21   will fix V0.30
Using ? * <addr> to see a memory location causes VAX/VMS version of simulator
to break down.

3560   V0.21   Fixed V0.30
The TDM serial port mode on serial port 2 is not implemented.

3561   V0.21   will fix V1.00
Inaccurate cycle times for all memory configurations in the CLK field except
for instructions running with internal program memory (RAM or ROM) and internal
dual-access data memory (RAM).

3562   V0.21   will fix V1.00
Memory-mapped wait state generator registers may be read and written;
however, cycle times on memory accesses to the corresponding addresses
will not reflect these wait states.

3615   V0.21   Fixed V0.30
An incorrectly signed result is displayed in the acc when a postive and
a negative value are multiplied together.

    Example:

              word1    .set   111h     SXM = 1
              *correlRe = fe00h

              LT   coorelRe
              MPY  #word1
              PAC

3632   V0.21   Fixed V0.30
ARP in STO is not popped when returning from an interrupt routine.

3703   V0.21   will fix V0.30
If LDP is changed prior to a (timer-) interrupt the old value is restored
instead of the new when the return is made from the interrupt.

3704   V0.21   will fix V0.30
When setting the TXNT bit in the IFR reg. and then executing the interrupt, the
XINT bit in the IMR reg. will be set when you branch to the interrupt vector.

3705   V0.21   will fix V0.30
SACL TREG1 prior to SATH or SATL will work in simulator even if it shouldn't.
It should be two cycles in between.

3706   V0.21   will fix V0.30
In the User's Guide the BITT instruction uses TREG2 to point out bit, but the
simulator seems to use TREG0.

3759   V0.21   will fix
If the NDX bit is set to 0 (C25 compatibility mode), all instructions which
modify AR0 should also modify ARCR and INDX.  Currently, the only instruction
which correctly updates the registers is the LAR instruction.
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