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* RELEASE 0.30 BUGLIST                                                        *
* Update - 10/25/91                                                           *
* This file contains a list of bugs in release 0.30 of the 320C50 simulator   *
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3797     V0.30  will fix next release
  When the LACC instruction has a shift value of 12, the reverse assembly
window doesn't display the instruction following the LACC.  The following
instruction is, however , executed correctly.

3852     V0.30  will fix next release
  The "win" command will return the error message "Window not found"
even though the correct window is selected.

3855     V0.30  will fix next release
  The SQRS instruction performs an unsigned multiply, instead of
a signed multiply as it should. This happens even if SXM has
been set.

3901     V0.30  will fix next release
  BRCR and BRAF do not get updated correctly when you single
step a RPTB loop.

3903     V0.30  will fix next release
  The ARB register sometimes will not be updated correctly.

3908     V0.30  will fix next release
  The MPYK # instruction does not fully sign extend the PREG
even when sign extension mode is set.

3966     V0.30  will fix next release
  The simulator incorrectly processes an SAR instruction in which the
uxiliary register is auto-incremented/decremented. The simulator
increments/decrements the register before storing its contents at
the destination address. It should not modify the register until
after the store.

e.g.    SAR ar1,*+    -or-  SAR ar1,*-

4086     V0.40  will fix next release
  If a loop contains code at the top to disable interrupts and code at the
bottom to re-enable inteerrupts, if an interrupt is pending when the code
reaches
the interrupt enable at the bottom of the loop, the simulator does not
branch to the interrupt service routine. Instead it increments the PC to
a location beyond the loop and continues to execute .

e.g.
bgidle: mar *-
        setc    intm
        lacl    *
        splk    #bgidle,*+
        clrc    intm
        bacc

4096     V0.30  will fix next release
  A simulated interrupt occurs during execution of the code fragment
listed below. In the ISR, the return address points to the NOP
statement.  On return from interrupt, the AR1 register has not been
modified -- that is, AR1 === 0x301, vice the expected 0xbff.  The
ISR has no effect on any of the auxiliary registers.

e.g.

        LAMM    AR7     ;;AR7 is 0xbfc, AR1 is 0x301
        ADD     #3      ;;  interrupt occurs here
        SAMM    AR1
        MAR     *,AR1
        NOP             ;; on retrun from interrupt ar1=0x301

4112     V0.30  will fix next release
  If an interrupt occurs during a RPTB sequence, such that address of
the last instruction of the block is address placed at TOS when the
vector is taken, then the RPTB will terminate incorrectly: if this
occurs once during the RPTB sequence, then the sequence will terminate
two iterations too early; and so forth.  When the erroneous termination
occurs, BRAF is left set.

This is easily demonstrated. Please refer to the test program listing
provided with this fax. Set breakpoint at the first NOP in the main
program and run the program.  When the break occurs, set IFR = 8
to force an interrupt.  Continue execution by single stepping.  The
RPTB will terminate as soon as BRCR decrements to zero, which is
incorrect, and BRAF will remain set.  If you force the interrupt twice
(at the indicated location), the sequence will terminate when BRCR
decrements to one, again with BRAF remaining set.  If you force the
interrupt every time the breakpoint is hit, the sequence will terminate
when BRCR is decmrented t0 3 - once again, with BRAF remaining set.

4113     V0.30  will fix next release
  A breakpoint on the last instruction of a RPTB sequence will cause BRCR
to decrement twice for each iteration of the sequence.

4138     V0.40  will fix next release
  There is a bug in the context save for interrupts in the C5x simulator.
If the interrupt service routine modifes ARP/ARB - the ARP/ARB may be
restored to incorrect value after return from interrupt is executed.

4199     V0.40  will fix next release
  The simulator flags an error of the operand of DMOV is a single port
Ram location. It should work for both single and Dual Ram.
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