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* RELEASE 0.40 BUGLIST                                                        *
* Update - 05/01/92                                                           *
*                                                                             *
* This file contains a list of bugs in release 0.40 of the 320C50 simulator   *
*                                                                             *
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				Part 1

4086     V0.40  will fix next release
  If a loop contains code at the top to disable interrupts and code at the

bottom to re-enable inteerrupts, if an interrupt is pending when the code

reaches the interrupt enable at the bottom of the loop, the simulator does not

branch to the interrupt service routine. Instead it increments the PC to
a location beyond the loop and continues to execute .

e.g.
bgidle: mar *-
	setc	intm
	lacl	*
	splk	#bgidle,*+
	clrc	intm
	bacc


4138     V0.40  will fix next release
  There is a bug in the context save for interrupts in the C5x simulator. 
If the interrupt service routine modifes ARP/ARB - the ARP/ARB may be 
restored to incorrect value after return from interrupt is executed.


4199     V0.40  will fix next release
  The simulator flags an error of the operand of DMOV is a single port
Ram location. It should work for both single and Dual Ram.


4475     V1.00  will fix next release
  NOTE THAT THE FOLLOWING BUG OCCURS ONLY UNDER VERY SPECIFIC CONDITIONS
HENCE  PLEASE CONFIRM WITH THE TOOLS GROUP, IF A CUSTOMER REPORTS A
PROBLEM WHICH SOUNDS SIMILAR TO THIS. - Thanks

If an interrupt occurs when a 2 word Branch/Call instruction is in the 
Execute phase of the pipeline and the first word of another 2 word 
Branch/Call instruction is in the Fetch phase, then the simulator yields
unpredictable results.

Eg:

PC ==>	B   23h, eq   ;  let's say a time interrupt will occur here
	BIT
	B 3445h

The pipelin would look like

	PC ==> Execute	:	B eq		==> TIM = 1, step TIM = 0
	       Read	:	<2nd word> (23h)
               Decode	:	BIT
	       Fetch	:	B

Now if you step, a timer interrupt occurs, and the simulator behaviour is
random.


Workaround:  Place a NOP between the two branch instructions.

	B	23h, eq 
	BIT
	NOP
	B 3445h


4518     V1.00  will fix next release
  When the last statement of a function is a call to another function the control
goes to the wrong place when the first function exits.

 e.g
	funct(a)
	int a;
	{
	    a+=10;
	    nextfun();
        }

This will cause control to break when funct() exits.

Workaround:  Put a dummy statement, (which is not a function call!!!) as 
	     the last statement in the function. For eg:

	     funct(a)
	     int a;
	     {
		a+=10;
		nextfun();
		a=a;        /* Dummy statement */
              }

	     Remember that this is required only if the last statement
	     in a function happens to be a function call to some other
	     function.


4563     V1.00  will fix next release
  NOTE: This is a new description for this bug!
The CNF bit is not handled properly in the simulator. You may note the
following things happening when the CNF bit is set.

1.  If you enable on-chip program RAM, by setting the CNF bit, the simulator 
does not display the on-chip RAM (0fe00h - 0ffffh), when a  "mem 0xfe00 @prog" 
or a  "dasm 0xfe00"  is entered from the command window.  The assembly 
program however can read/write the on-chip RAM without any problem; only 
the contents will not be displayed.

2.  The simulator will not perform a memory fill command on the area of 
memory 0xfe00-0xffff.  (This will happen regardless of value of CNF bit.)

3.  If CNF bit is set and a BLKDP instruction is used to transfer data
to the locations 0xfe00-0xffff, the simulator may give illegal memory
access errors.


4637     V1.00  will fix next release
  Note: PC Windows version only!!!

 In the windows version of the simulator if you perform a memory delete
"MD" it generates a windows UNRECOVERABLE APPLICATION ERROR.

 Workaround:  Perform a memory reset "MR" and the use memory add, "MA"
	      to define wanted memory.


4641     V1.00  will fix next release
  The simulator fails to reset the BRAF bit after executing a RPTB with
an execution size of 1, i.e. BRCR=0.


4646     V1.00  will fix next release
  If the NDX bit is 0, the instruction "mar *,ar0" overwrites the contents
of INDX with the contents of AR0. "mar *,ar0" does not update AR0, it
updates only ARP.  This is a bug.

For eg

	lacc	#20
	samm	INDX
	mar	*,ar0   ; Here the INDX becomes Zero.

Workaround:  Move the "mar *,ar0", instruction above any instruction updating
	     INDX.

	     mar	*,ar0
	     lacc	#20
	     samm	INDX


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