-------------------------------------------------------------------------------
*  RELEASE 0.12 BUGLIST                                                       *
*  Update - 10/29/90                                                          *
*  This file contains a list of bugs in the release 0.12 of the 320C50        *
*  simulator.                                                                 *
-------------------------------------------------------------------------------
SIMULATOR
-------------------------------------------------------------------------------
3135   V0.12   Fixed V0.20
Registers ST0,ST1,PMST,TREG1 & TREG2 are not saved on interrupt.

3224   V0.12   Fixed V0.20
Changing the data page pointer with the simulator DP command does not update
the reverse-assembler address.

3227   V0.12   Fixed V0.20
The following memory ranges in data space are not implemented as defined
by Spec 2.5:
             100-2ffh   data memory when CNF=0
             100-2ffh   reserved when CNF=1
             400-4ffh   data memory
             500-5ffh   reserved in data space

3228   V0.12   Fixed V0.20
The blocks of RAM B0 and B1 are 512 words of RAM, not 256.

3229   V0.12   Fixed V0.20
The on-chip single access RAM on the C50 in 9k words, not 8k words.

3230   V0.12   Fixed V0.20
The block repeat active flag (BRAF) is improperly cleared on a block repeat.
It is being cleared when the blockrepeat counter register (BRCR) decrements
to zero.  It should be cleared when the BRCR decrements below zero.  In
addition, the PMST register is improperly reset to zero at the completion of
a block repeat (only the BRAF should be cleared).

3231   V0.12   Fixed V0.20
The external interrupts are presently numbered INT0-INT2 instead of INT1-INT3
as they should be.

3234   V0.12   Fixed V0.20
Circular buffers should only work with an auxiliary register modification
other than zero.  The simulator allows an AR operation with no AR
modification to load CBSR into the current AR.  The value should only be
loaded if the current AR=CBER and a non-zero AR modification occurs.

3287   V0.12   Fixed V0.20
When bit 0 in PMST register is reset by executing a repeat block, all the
bits are reset to 0.  For example, enable the 3 T-REG and index register
option.  After a repeat block is finished everthing related to the PMST
register is reset.

3429   V0.12   Fixed V0.20
The RPTB instruction (repeat block) does not work unless it contains at least
3 instruction words.

3430   V0.12   Fixed V0.20
BCND BIO instructions branch when BIO = 1, but branch should occur when
BIO = 0.

3431   V0.12   Fixed V0.20
The SPLK instruction loops forever if used in a circular buffer in Single
in Single Access RAM.  For example:
        SLPK    #800,CBSR1
        SLPK    #800,CBSR1
        LAR      AR1,#800h
        SLPK    #(1<<3)+1,CBCR
        SLPK    #1,*+           ; Simulator gets stuck here.
        LAC      *+
        LAC      *+


3432   V0.12   Fixed V0.20
The BANZD instruction does not work.

3433   V0.12   Fixed V0.20
The RPT instruction does not work for values greater than 100 hex.

3434   V0.12   Fixed V0.20
MAR instruction generates  >>ERROR ACCESSED RESERVED MEMORY LOCATION
if the current auxillary register value is not a valid memory location.
But the MAR instruction does not access memory.

3435   V0.12   Fixed V0.20
Simulator does not load .data section.

3447   V0.12   Fixed V0.20
Conditional delayed branches (BCNDD) reset ARP=0 when the branch is taken
(that is, when the condition=true).
-------------------------------------------------------------------------------
*  RELEASE 0.21 BUGLIST                                                       *
*  Update - 2/5/91                                                            *
*  This file contains a list of bugs in the release 0.21 of the 320C50        *
*  simulator.                                                                 *
-------------------------------------------------------------------------------
SIMULATOR
-------------------------------------------------------------------------------
3505   V0.21   Fixed V0.30
After the repeat instructions have loaded registers BRCR and RPTC they
cannot be modified either from the CPU register window or by user's program
code.

3506   V0.21   Fixed V0.30
Clearing the PMST register BRAF bit (Block repeat active flag) has no effect
on the execution of the repeat block.

3507   V0.21   Fixed V0.30
The simulator allows repeat blocks of any length, but RPTB should not work
with blocks less than 3 words long.

3508   V0.21   Fixed V0.30
The BRCH register must be loaded at least 2 instructions prior to execution
of the RPTB instruction.  Also, RPT and RPTZ instructions using a direct
address repeat count must load the data memory location at two cycles
prior to the RPT instruction.  (Repeat instructions with immediate address
repeat count operate as expected).

3509   V0.21   Fixed V0.30
A repeat instruction, RPT, with a specified repeat value of 0 (repeat once)
does not operate correctly when a 2 word instruction is specified.
For example:
                RPT  #0
                BLDD #300,*+

3510   V0.21   Fixed V0.30
The delayed-call instruction cannot be used 2 words before the end of a
block repeat.  The simulator executes an infinite block repeat loop.
For example:
                LOOPHERE   RPTB  ENDLOOP-1
                           LACC  DAT1
                           CALLD TEST
                           ADD   DAT2
                           SACL  DAT1
                ENDLOOP

3511   V0.21   Fixed V0.30
Instructions referencing the PMST register are effected immediately by changes
to PMST when instead, they should not be effected until after a delay of 2
instuction cycles following the change.  That is, instructions should not be
effected if the PMST register is changed while the referencing instruction is
in the pipeline.

3512   V0.21   Fixed V0.30
The disassembler follows the C25 rather than the C5x mneumonic conventions in
some cases:
                                disassembles
                ADD   dma,16  ----------------> ADDH  dma
                AND   dsm,16  ----------------> ANDH  dma
                OR    dsm,16  ----------------> ORH   dma
                SUB   dsm,16  ----------------> SUBH  dma
                XOR   dsm,16  ----------------> XORH  dma
                LACC  dsm,16  ----------------> ZALH  dma
                LACL #k       ----------------> LAC   #k
                LST  #k, xxh  ----------------> LST2  xxh
                LST  #0, xxh  ----------------> LST1  xxh
                MAR  *,ARx    ----------------> LARP  ARx
                SST  #1, xxh  ----------------> SST1  xxh
                SST  #0, xxh  ----------------> SST2  xxh

3532   V0.21   Fixed V0.30
BANZ instruction does not work properly. Therefore c_int0 fails to initialize C
variables when using -c option.  example:
            .text
     MAIN   LDP     #0             ;ar0 = 0 initially
            MAR     *,AR0
            LAR     AR0,#60h
            LAR     AR0,*          ;ar0 <- (60h)
            BANZ    JP1,*-         ;Branch not take even when (60h!=0)
            NOP
            NOP
            NOP
            NOP
     SPIN   B       SPIN
            NOP
            NOP
     JP1    NOP
     SPIN2  B       SPIN2

Workaround:  Compile with -cr option, this works.

3549   V0.21   Fixed V0.30
The instructions OPL, APL, and XPL should clear the TC bit to 0 if the
result of the operation is 0.  Otherwise, the TC bit should be set to 1.
These instructions have no effect on the TC bit in the simulator Versions
0.12 and 0.21

3557   V0.21   will fix V0.30
Using ? * <addr> to see a memory location causes VAX/VMS version of simulator
to break down.

3560   V0.21   Fixed V0.30
The TDM serial port mode on serial port 2 is not implemented.

3561   V0.21   will fix V1.00
Inaccurate cycle times for all memory configurations in the CLK field except
for instructions running with internal program memory (RAM or ROM) and internal
dual-access data memory (RAM).

3562   V0.21   will fix V1.00
Memory-mapped wait state generator registers may be read and written;
however, cycle times on memory accesses to the corresponding addresses
will not reflect these wait states.

3615   V0.21   Fixed V0.30
An incorrectly signed result is displayed in the acc when a postive and
a negative value are multiplied together.

    Example:

              word1    .set   111h     SXM = 1
              *correlRe = fe00h

              LT   coorelRe
              MPY  #word1
              PAC

3632   V0.21   Fixed V0.30
ARP in STO is not popped when returning from an interrupt routine.

3703   V0.21   will fix V0.30
If LDP is changed prior to a (timer-) interrupt the old value is restored
instead of the new when the return is made from the interrupt.

3704   V0.21   will fix V0.30
When setting the TXNT bit in the IFR reg. and then executing the interrupt, the
XINT bit in the IMR reg. will be set when you branch to the interrupt vector.

3705   V0.21   will fix V0.30
SACL TREG1 prior to SATH or SATL will work in simulator even if it shouldn't.
It should be two cycles in between.

3706   V0.21   will fix V0.30
In the User's Guide the BITT instruction uses TREG2 to point out bit, but the
simulator seems to use TREG0.

3759   V0.21   will fix
If the NDX bit is set to 0 (C25 compatibility mode), all instructions which
modify AR0 should also modify ARCR and INDX.  Currently, the only instruction
which correctly updates the registers is the LAR instruction.
-------------------------------------------------------------------------------
* RELEASE 0.30 BUGLIST                                                        *
* Update - 10/25/91                                                           *
* This file contains a list of bugs in release 0.30 of the 320C50 simulator   *
-------------------------------------------------------------------------------
3797     V0.30  will fix next release
  When the LACC instruction has a shift value of 12, the reverse assembly
window doesn't display the instruction following the LACC.  The following
instruction is, however , executed correctly.

3852     V0.30  will fix next release
  The "win" command will return the error message "Window not found"
even though the correct window is selected.

3855     V0.30  will fix next release
  The SQRS instruction performs an unsigned multiply, instead of
a signed multiply as it should. This happens even if SXM has
been set.

3901     V0.30  will fix next release
  BRCR and BRAF do not get updated correctly when you single
step a RPTB loop.

3903     V0.30  will fix next release
  The ARB register sometimes will not be updated correctly.

3908     V0.30  will fix next release
  The MPYK # instruction does not fully sign extend the PREG
even when sign extension mode is set.

3966     V0.30  will fix next release
  The simulator incorrectly processes an SAR instruction in which the
uxiliary register is auto-incremented/decremented. The simulator
increments/decrements the register before storing its contents at
the destination address. It should not modify the register until
after the store.

e.g.    SAR ar1,*+    -or-  SAR ar1,*-

4086     V0.40  will fix next release
  If a loop contains code at the top to disable interrupts and code at the
bottom to re-enable inteerrupts, if an interrupt is pending when the code
reaches
the interrupt enable at the bottom of the loop, the simulator does not
branch to the interrupt service routine. Instead it increments the PC to
a location beyond the loop and continues to execute .

e.g.
bgidle: mar *-
        setc    intm
        lacl    *
        splk    #bgidle,*+
        clrc    intm
        bacc

4096     V0.30  will fix next release
  A simulated interrupt occurs during execution of the code fragment
listed below. In the ISR, the return address points to the NOP
statement.  On return from interrupt, the AR1 register has not been
modified -- that is, AR1 === 0x301, vice the expected 0xbff.  The
ISR has no effect on any of the auxiliary registers.

e.g.

        LAMM    AR7     ;;AR7 is 0xbfc, AR1 is 0x301
        ADD     #3      ;;  interrupt occurs here
        SAMM    AR1
        MAR     *,AR1
        NOP             ;; on retrun from interrupt ar1=0x301

4112     V0.30  will fix next release
  If an interrupt occurs during a RPTB sequence, such that address of
the last instruction of the block is address placed at TOS when the
vector is taken, then the RPTB will terminate incorrectly: if this
occurs once during the RPTB sequence, then the sequence will terminate
two iterations too early; and so forth.  When the erroneous termination
occurs, BRAF is left set.

This is easily demonstrated. Please refer to the test program listing
provided with this fax. Set breakpoint at the first NOP in the main
program and run the program.  When the break occurs, set IFR = 8
to force an interrupt.  Continue execution by single stepping.  The
RPTB will terminate as soon as BRCR decrements to zero, which is
incorrect, and BRAF will remain set.  If you force the interrupt twice
(at the indicated location), the sequence will terminate when BRCR
decrements to one, again with BRAF remaining set.  If you force the
interrupt every time the breakpoint is hit, the sequence will terminate
when BRCR is decmrented t0 3 - once again, with BRAF remaining set.

4113     V0.30  will fix next release
  A breakpoint on the last instruction of a RPTB sequence will cause BRCR
to decrement twice for each iteration of the sequence.

4138     V0.40  will fix next release
  There is a bug in the context save for interrupts in the C5x simulator.
If the interrupt service routine modifes ARP/ARB - the ARP/ARB may be
restored to incorrect value after return from interrupt is executed.

4199     V0.40  will fix next release
  The simulator flags an error of the operand of DMOV is a single port
Ram location. It should work for both single and Dual Ram.
-------------------------------------------------------------------------------
* RELEASE 0.40 BUGLIST                                                        *
* Update - 05/01/92                                                           *
*                                                                             *
* This file contains a list of bugs in release 0.40 of the 320C50 simulator   *
*                                                                             *
-------------------------------------------------------------------------------

4086     V0.40  will fix next release
  If a loop contains code at the top to disable interrupts and code at the

bottom to re-enable inteerrupts, if an interrupt is pending when the code

reaches the interrupt enable at the bottom of the loop, the simulator does not

branch to the interrupt service routine. Instead it increments the PC to
a location beyond the loop and continues to execute .

e.g.
bgidle: mar *-
	setc	intm
	lacl	*
	splk	#bgidle,*+
	clrc	intm
	bacc


4138     V0.40  will fix next release
  There is a bug in the context save for interrupts in the C5x simulator. 
If the interrupt service routine modifes ARP/ARB - the ARP/ARB may be 
restored to incorrect value after return from interrupt is executed.


4199     V0.40  will fix next release
  The simulator flags an error of the operand of DMOV is a single port
Ram location. It should work for both single and Dual Ram.


4475     V1.00  will fix next release
  NOTE THAT THE FOLLOWING BUG OCCURS ONLY UNDER VERY SPECIFIC CONDITIONS
HENCE  PLEASE CONFIRM WITH THE TOOLS GROUP, IF A CUSTOMER REPORTS A
PROBLEM WHICH SOUNDS SIMILAR TO THIS. - Thanks

If an interrupt occurs when a 2 word Branch/Call instruction is in the 
Execute phase of the pipeline and the first word of another 2 word 
Branch/Call instruction is in the Fetch phase, then the simulator yields
unpredictable results.

Eg:

PC ==>	B   23h, eq   ;  let's say a time interrupt will occur here
	BIT
	B 3445h

The pipelin would look like

	PC ==> Execute	:	B eq		==> TIM = 1, step TIM = 0
	       Read	:	<2nd word> (23h)
               Decode	:	BIT
	       Fetch	:	B

Now if you step, a timer interrupt occurs, and the simulator behaviour is
random.


Workaround:  Place a NOP between the two branch instructions.

	B	23h, eq 
	BIT
	NOP
	B 3445h


4518     V1.00  will fix next release
  When the last statement of a function is a call to another function the control
goes to the wrong place when the first function exits.

 e.g
	funct(a)
	int a;
	{
	    a+=10;
	    nextfun();
        }

This will cause control to break when funct() exits.

Workaround:  Put a dummy statement, (which is not a function call!!!) as 
	     the last statement in the function. For eg:

	     funct(a)
	     int a;
	     {
		a+=10;
		nextfun();
		a=a;        /* Dummy statement */
              }

	     Remember that this is required only if the last statement
	     in a function happens to be a function call to some other
	     function.


4563     V1.00  will fix next release
  NOTE: This is a new description for this bug!
The CNF bit is not handled properly in the simulator. You may note the
following things happening when the CNF bit is set.

1.  If you enable on-chip program RAM, by setting the CNF bit, the simulator 
does not display the on-chip RAM (0fe00h - 0ffffh), when a  "mem 0xfe00 @prog" 
or a  "dasm 0xfe00"  is entered from the command window.  The assembly 
program however can read/write the on-chip RAM without any problem; only 
the contents will not be displayed.

2.  The simulator will not perform a memory fill command on the area of 
memory 0xfe00-0xffff.  (This will happen regardless of value of CNF bit.)

3.  If CNF bit is set and a BLKDP instruction is used to transfer data
to the locations 0xfe00-0xffff, the simulator may give illegal memory
access errors.


4637     V1.00  will fix next release
  Note: PC Windows version only!!!

 In the windows version of the simulator if you perform a memory delete
"MD" it generates a windows UNRECOVERABLE APPLICATION ERROR.

 Workaround:  Perform a memory reset "MR" and the use memory add, "MA"
	      to define wanted memory.


4641     V1.00  will fix next release
  The simulator fails to reset the BRAF bit after executing a RPTB with
an execution size of 1, i.e. BRCR=0.


4646     V1.00  will fix next release
  If the NDX bit is 0, the instruction "mar *,ar0" overwrites the contents
of INDX with the contents of AR0. "mar *,ar0" does not update AR0, it
updates only ARP.  This is a bug.

For eg

	lacc	#20
	samm	INDX
	mar	*,ar0   ; Here the INDX becomes Zero.

Workaround:  Move the "mar *,ar0", instruction above any instruction updating
	     INDX.

	     mar	*,ar0
	     lacc	#20
	     samm	INDX
-------------------------------------------------------------------------------
