From: DSP Hotline

Subject: 320C50 Simulator Bug List

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* RELEASE 1.xx BUGLIST                                                        *
* Update - 11/18/94                                                           *
*                                                                             *
* This file contains a list of bugs in the release 1.xx of the 320C50         *
* Simulator                                                                   *
*                                                                             *
* All bugs will be fixed in the next production release unless othwerwise     *
* indicated. There will sometimes be references to internal versions in       *
* this list. For that reason you must always refer to the release status      *
* information (published every two weeks) to verify the availability of a     *
* specific revision.                                                          *
*                                                                             *
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				Part 1

4922     V1.11  will fix next release
  Note: This problem occurs under a very specific set of circumstances.
      If you suspect that you have encountered this problem, please
      check with tools group for confirmation.

When an interrupt occurs when a B/CALL is in the Decode phase and any
instruction which updates AR in the READ phase, then the AR modification
occurs twice.

For eg, if an interrupt occurs when the pipeline scenario is :

     MAR     *,AR3     ===>>>>     -X-
     ADRK    #2     ===>>>> -R-
     B          ===>>>> -D-
     <addr>          ===>>>> -F-

Workaround:  Place a NOP between the ADDRK and the B instructions.


5006     V1.11  will fix next release
  The LTD instruction does not perform the Data move, when the Dual access
RAM is mapped into the Data space. (0x800 - 0x2bff in C50, 0x800 - bff in
the case of C51). It gives an "Ilegal memory access" error message.


5026     V1.11  will fix next release
  If an interrupt occurs when a RPT instruction is in the READ or DECODE
phase of the pipeline, the simulator gives a non repeatable instruction
error message, which is wrong. The simulator should not recognize the
interrupt until the RPT loop goes out of the pipeline.


5097     V1.11  will fix next release
  The C5x memory-mapped I/O registers , locations 0x50 - 0x5F, cannot
be READ using any instructions that normally access memory, i.e.
LACC, LAMM, etc.  However the instruction IN does read these addresses
correctly.

Note: Writes to these locations function normally it is only reads
      that are affected.

Workaround: In the siminit.cmd map these locations to I/O address
         space (page 2) rather than data address space (page 1).

         i.e.

         ma 0x50,2,1,iport
         mc 0x50,2,"input",read


5109     V1.11  will fix next release
  The simulator may generate a corrupt call stack message while stepping a
C function - whose body consists solely of ASM statements generated by
using asm(" ").


Workaround:  Include at least one dummy C statement;

          i.e.

          void function(void) 
          {

          int i=0;
          asm("  NOP  ");
          asm("  NOP  ");
          }


5199     V1.11  will fix next release
  The memory save command "ms" does not work if the memory range specified 
is on page 0 (program mem), and the corresponding memory address/range in
page 1 (data mem) is either reserved or unconfigured memory.


Workaround: If the data addresses in data memory are not reserved, then
         configure the memory on page 1 as well, by using memory 
         add commands.


5298     V1.11  will fix next release
  The simulator incorrectly flushes the pipeline by executing the two
intstructions following and IDLE instruction, before branching to
the interrupt vector.


5411     V1.11  will fix next release
  The simulator errs in using the contents of AR0 for the increment
in the NORM instruction (i.e. NORM *0+ , NORM *0-) instead of the 
value stored in the INDX register.


Workaround:  Place desired increment in AR0.


5604     V1.11  will fix in V1.12
  When using an IOPORT at any address in the range 0x31 to 0x51 that has been 
properly mapped on to page 2, the simulator errs in returning the message
"illegal memory access" if you attempt to write data to that address using
the OUT instruction.  

WORK AROUND
===========
Map the I/O port to an address outside of the above mentioned range that
is not being used.  The best suggestion would be to use something above 0x60.


5607     V1.11  will fix in V1.12
  The simulator "fill" command has a maximum range of 4096 (0x1000)
for the length parameter.

WORK AROUND
===========
When attempting to fill memory in the simulator, use the fill
command to fill small segments of memory 4095 words (0xfff)
or less.


5687     V1.11  will fix in V1.20
  Trying to map files to data space locations in the C5x simulator.
This does not seem to work.  Mapping to I/O space does however.

This seems consistent with the C5x Source Debugger documentation.
The C3x simulator does map memory locations, it would seem that
the C5x simulator could as well.

***The current versions of the simulator does not allow files to 
   be connected to Data memory locations. Files can be connected 
   to only I/O Ports (page 2) and the memory mapped I/O port 
   locations, 0x50-0x5f. However, the latest version of the 
   Simulator V1.20, which is under production now, will let files 
   to be connected to data memory locations too.


5707     V(current)  will fix next release
  The RRDY/XRDY bits do NOT get cleared after a read/write from the DRR/DXR.


5757     V1.20  will fix next release
  The pseudo register TICID and ITCIP do not seem to be
displayed correctly.  This register worked correctly in
this same code with resion 1.11.  It seems that random
values are displayed since the timer register doesn't
count down and the period register changes when I am not
changing it.

WORK AROUND/SOLUTION:
=====================
  V1.20 of the C5X Simulator simulates external interrupts using the
  External Event Simulation module and not through the old scheme of
  pseudo registers TIC1T and TIC1P.  TIC1T and TIC1P should not be 
  supported anymore; in the sense that the simulator should give an 
  error while using these registers, rather than keeping quiet and 
  showing spurious values later on.  This will be corrected in a 
  future release.


5796     V1.20  will fix next release
  When an interrupt trap is taken and an IDLE instruction is in the
READ or DECODE phase of the pipeline, the simulator pushes 0xffff
as the RETURN address onto the stack.

WORK AROUND/SOLUTION:
=====================
Work around the problem by replacing the IDLE with NOPs.

The problem is due to the way IDLE is implemented.  As you can see 
when the interrupt is ready to be taken, the instruction IDLE is in 
the READ phase. (next to OPL instruction). The way IDLE works is as 
follows: When IDLE is in the DECODE phase, the pipeline is frozen and 
NOPs are filled in the PIPE until an interrupt is recognized. So when
OPL is in the Exe phase and IDLE is in the READ phase, the remaining 
part of the pipeline are filled with NOPs introduced by the simulator. 
When a simulator introduces NOP, just to distinguish if it is NOP in 
the user code or a NOP jammed by the simulator, the simulator fills 
the address from where the instruction is read as -1. Now an interrupt 
happens and the simulator blindly jams the INTR in the place where the
NOP with -1 address was, and pushes the address where the jammed INTR
was onto the stack. Hence -1 gets pushed onto the stacK!!


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4930     V(current)  will fix next release
  Note:  The maximum number of files that can be connected to an I/O
port in the simulator via "mc" commands is 14.  This is a simulator
feature resulting from a limitation on the number of files that
are allocated to any one program under DOS.


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