
                    TMP320C30 PG2 TIMIMG CHARACTERIZATION       MHR  11/28/89

        There has been some timing changes in the 320C30 as specified on pages
A5 to A25 in the 320C30 User's Guide. Most of the timing changes are minor.
However, there is one major change that can effect clients already designing
with the part: the memory access time has increased by 5ns as signified by the
Astericks below (*). If the user designed to the old spec, he will either need
a faster memory, a 5ns faster decode, or a slowdown on the input clock by 5ns.

The following changes and additions should also be noted:

    O  Icc for the device is specified as 250mA typical, down from 300mA
       typical. The max for Icc has been set at 600mA.

    O  Temperature testing has changed to 85 C case from 75 C ambient.

    O  The read write (R/W-) and external read write (XR/W-) signals which were
       specified to be inactive (high) during reset have been respecified to go
       tri-state during reset, meaning that customers designing to the previous
       spec could have some data could be overwritten during a reset. To avoid
       this problem simply attach 20K pullup resistors to these signals.

    O  The few silicon errors that have been found on the 320C30 can be found
       under "OTHER" on the third generation under m /320.

Unless otherwise noted, the new spec timings are the same as the old spec
timings:

                          SWITCHING CHARACTERISTICS
                          -------------------------
The following specs should be added to the switching characteristics on page
A-5 in the User's Guide.

                 CLOCK TIMING                 SPEC
                 ------------                 ----
                  tf(H3)                       3ns
                  tw(H3L)                   tcCI-6ns
                  tw(H3H)                   tcCI-7ns
                  tr(H3)                       4ns



                       PRIMARY BUS MEMORY TIMINGS
                       --------------------------
The timings currently in the user's guide are for both the Primary and
Expansion busses (page A-5). Becasue of changes in their timing, the two specs
should be seperated out.

        SPEC                                              NEW
PAGE    No.      CLOCK TIMING                 SPEC        SPEC
----    ----     ------------                 ----        ----
A-5     11       td(H1L-SL)                  10ns
        12       td(H1L-SH)                  10ns
        13       td(H1H-RWL)                 10ns
      * 14       td(H1L-A)   (READ)          10ns        14ns (+4ns)  +5ns
                 td(H1H-A)   (WRITE)         ??ns        18ns        > access
      * 15       tsu(D)R                     15ns        16ns (+1ns)   time
        16       th(D)                        0ns
        17       tsu(RDY)                     8ns
A-6     18       th(RDY)                      0ns
        19       td(H1H-RWH)                 10ns
        20       tv(D)W                      20ns
        21       th(D)WH                      0ns
        21       th(D)WL                      0ns



                 EXPANSION BUS MEMORY TIMINGS (MSTRB)
                 ------------------------------------
See note above.

        SPEC                                              NEW
PAGE    No.      CLOCK TIMING                 SPEC        SPEC
----    ----     ------------                 ----        ----
A-5     11       td(H1L-(M)SL)                10ns
        12       td(H1L-(M)SH)                10ns
        13       td(H1H-(IO)RWL)              10ns
        14       td(H1L-(IO)A)   RD           10ns
                 td(H1H-(IO)A)   WR           ??ns        25ns
        15       tsu((IO)D)R)                 15ns        18ns
        16       th((IO)DR)                    0ns
        17       tsu((IO)RDY)                  8ns         9ns
        18       th((IO)RDY)                   0ns
A-6     19       td(H1H-(IO)RWH)              10ns
        20       tv((IO)D)W)                  20ns
        21       th((IO)D)WH                   0ns
        21       th((IO)D)WL                   0ns


                  EXPANSION BUS IO TIMINGS  (IOSTRB)
                  ----------------------------------
One timing change and 1 misprint in the book should be noted.

        SPEC                                              NEW
PAGE    No.      CLOCK TIMING                 SPEC        SPEC
----    ----     ------------                 ----        ----
A-9     17.1     tsu(IORDY)                    8ns        9ns
        21.1     th(IOD)WH                     0ns
        21.1     th(IOD)WL                     0ns


                    RESET/INTERRUPT TIMINGS
                    -----------------------
The following changes should be noted.

        SPEC                                              NEW
PAGE    No.      CLOCK TIMING                 SPEC        SPEC
----    ----     ------------                 ----        ----
A-18     2       td(CLKINH-H1H)               15ns        16ns
         5       td(CLKINH-H3L)               15ns        16ns


                SERIAL PORT GENERAL PURPOSE I/O TIMINGS
                ---------------------------------------
The following timings are absent in the present version of the User's Guide:

                 CLOCK TIMING                 SPEC
                 ------------                 ----
                 td(H1H-CLK)XGPIO             10ns
                 td(H1H-CLK)RGPIO             10ns
                 td(H1H-FSX)GPIO              10ns
                 td(H1H-FSR)GPIO              10ns
                 td(H1H-DX)GPIO               10ns
                 td(H1H-DR)GPIO               10ns
                 tsu(CLK)XGPIO                10ns
                 tsu(CLK)RGPIO                10ns
                 tsu(FSX)GPIO                 10ns
                 tsu(FSR)GPIO                 10ns
                 tsu(D)XGPIO                  10ns
                 tsu(D)RGPIO                  10ns
                 th(CLK)XGPIO                  0ns
                 th(CLK)RGPIO                  0ns
                 th(FSX)GPIO                   0ns
                 th(FSR)GPIO                   0ns
                 th(D)XGPIO                    0ns
                 th(D)RGPIO                    0ns


                     HOLD/HOLDA TIMINGS
                     ------------------
The following changes should be noted:

        SPEC                                              NEW
PAGE    No.      CLOCK TIMING                 SPEC        SPEC
----    ----     ------------                 ----        ----
A-25     3       tv(HOLDA)L                   10ns
         3       tv(HOLDA)H                   10ns
         6       tw(HOLDA)                     tcH        tcH-5


            EXTERNAL FLAGS TIMINGS  (INTERLOCKED OPERATIONS)
            ------------------------------------------------
The following changes should be made:

        SPEC                                              NEW
PAGE    No.      CLOCK TIMING                 SPEC        SPEC
----    ----     ------------                 ----        ----
A-11    1        ts(H3H-XF0L) LDII            10ns        15ns
        2        tsu(XF1)     LDII             8ns        10ns
A-12    1        td(H3H-XF0H) STII            10ns        15ns
A-13    1        td(H3H-XF0L) SIGI            10ns        15ns
        2        td(H3H-XF0H) SIGI            10ns        15ns
        3        tsu(XF1)  SIGI                8ns        10ns
A-16    1        td(H3H-XFIO)                 10ns        15ns


                          TIMER TIMINGS
                          -------------
The following specs are absent in the present version of the User's Guide:

                 CLOCK TIMING                 SPEC
                 ------------                 ----
                 tsu(TCLK)                    12ns
                 ts(TCLK)                      0ns
                 td(TCLK)                     10ns
                 tsu(TCLK)GPIO                12ns
                 th(TCLK)GPIO                  0ns
                 td(TCLK)GPIO                 10ns


                     SERIAL PORT TIMINGS
                     -------------------
Three changes should be noted:

        SPEC                                              NEW
PAGE    No.      CLOCK TIMING                 SPEC        SPEC
----    ----     ------------                 ----        ----
A-24     3       tw(SCK)RL(ext)              tcH+5ns      +12ns
         8       th(DR)(int)                   -5ns       -10ns
        11       th(FS)(int)                   -5ns       -10ns

