
			TMX320C5x silicon errata
			Rev 2.x silicon (Document Revision 2.0)
                        Last Modified: 10/08/93

Silicon revision 2.x of C5X that includes TMx320C50, TMx320C51, TMx320C52,
TMx320C53, and TMx320C53SX have the following problems.  Each problem is
described and an appropriate work around is suggested.



Problem 1: The OUT instruction may corrupt some memory map registers.

The I/O space addresses from 20h to 4Fh are not properly decoded.  Whenever the
case of writing to this I/O block occurs the internal data memory from 20h to
4Fh is also accessed.  Thus the OUT instruction using these port addresses will
also overwrite the memory map registers that between 20h and 4Fh. However, there
is no problem with the sixteen memory-mapped port addresses in the range 50h to
5Fh. The following map identifies the problem address in I/O space.



                                 I/O
			 0000h _________
			      |         |
			      | Valid   |
			 001Fh|         |
			 0020h|---------|
			      | Invalid |
			 004Fh|---------|
			 0050h|         |
			      | Valid   |
			      |         |
			 FFFFh|_________|

                           C5X I/O Space Map



Work around:
Avoid using the I/O space port addresses 20h to 4Fh.

WILL BE FIXED IN LATER REVISION


Problem 2: On the TDM port, the TADD of an empty slot drives low.

According to the User's Guide, an empty slot is defined by the following two
cases: 1) when no device has TCSR (TDM Channel Select Register) configured to
transmit in that slot (i.e., no 1's in TCSR).  2) when the slot is configured
to transmit, but the TDXR (TDM Data Transmit Register) has been writted a new
data for transmit. Typically, the TADD line should be in high impedance for an
empty slot. However, the TADD line is pulled low internally in the second case
mentioned above.



Work around:
If the high impedance is expected on TADD, put 0's in the corresponding bits in
the TCSR.

WILL BE FIXED IN LATER REVISION


Problem 3: When the TDM port is reset, external TFRM and TCLK may corr          upt the
           TDAT line.

After the TDM serial port was reset by XRST, the data in the first several
frames are shifted sometimes.  This happens when the XRST and the external TFRM
pulse occur simultaneously and on the falling edge of TCLK (see figure below).

                 __    __    __    __    __    __    __    __
      TCLK    __|  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__
              _________________       __________________________
      XRST                     |_____|
                            _______________
      TFRM    _____________|               |_____________________



Work around in software:
For the normal software reset, pull the TRAD register to check the current slot
(bits 13-11) then reset the TDM port after first 2 slots (such as slot 4). This
will prevent the XRST and external TFRM occurring simultaneously.
In the IDLE2 mode, the device will freeze the status of TDM port and continue
after coming out of the power down mode. Thus the TCSR has to be cleared before
it get into the IDLE2 mode. Otherwise the slot counter will be corrupted after
processor wakes up. Since the TCSR will not update until next frame, it should
clear a frame before IDLE2 executes. Wait for second TFRM pulse after the
processor comes out of IDLE2 mode to initialize TCSR. Then reset the TDM port
after first 2 slots. Following is a simple example code to reset TDM port at
slot 4.



            SPLK   #0h,TCSR       ; clear TCSR before reset TDM port
            RPT    #lk            ; waif for one more frame to update the
            NOP                   ; the TCSR. The lk should equal the frame's
                                  ; period.
********************************************************
*  Ready to reset TDM port or step into IDLE2 mode     *
********************************************************
;           IDLE2                 ; get into IDLE2 mode
            CALL   TDMINIT        ; or reset TDM port
             .
             .
             .
TDMINIT:
;           RPT    #lk            ; If comes out of IDLE2 mode, wait for
;           NOP                   ; 2nd TFRM pulse
CHK:        LAMM   TRAD           ; Load TRAD Reg to chek bit 13-11 for
            OR     #3800h         ; current slot information.
            SUB    #2000h         ; If it is slot 4 then reset TDM port
            BCND   CHK,NEQ
            SPLK   #0039h,TSPC    ; put TDM port in reset
            SPLK   #00f9h,TSPC    ; pull TDM port out of reset
            RET


WILL BE FIXED IN LATER REVISION
