Revision date   June27th, 1995

Disclaimer:     These design files are for illustrative
                purposes only and are included to illustrate the PCI
                controller design. The equations have been simulated
                and are believed correct. The schematics have not been
                simulated.
                However, actual implementation will vary depending on the 
                design needs. Xilinx is not responsible for any conficts 
                that may exist between this design and the PCI Local Bus
                Specification.

                Please email any comments bug reports etc to pci@xilinx.com
                
PCI_VHDL.ZIP:   VHDL source code for XC73144 Target Interface design in 
                application note "Designing Flexible PCI Interfaces
                with Xilinx EPLDs."

PCI_ABEL.ZIP    ABEL source code for XC73108 and XC7354 designs in 
                application note "Designing Flexible PCI Interfaces
                with Xilinx EPLDs."

                TARGET.ABL ABEL source code of UPDATED Target interface
                PARITY.ABL ABEL source code of UPDATED Target interface

PCI_V.ZIP       Verilog/HDL source code for XC3164 designs in 
                application note "Fully Compliant PCI Interface in
                XC3164A-2."

3100ACKL.ZIP    XC31OOA-2 PCI Component Electrical Checklist (WORD v6.0)
                XC3100A-1 silicon is now available.

7300CKL.ZIP     XC730O-10 PCI Component Electrical Checklist (WORD v6.0)

REV1E.ZIP       Viewlogic version of Verilog/HDL source code for XC3164
                designs in application note "Fully Compliant PCI
                Interface in XC3164A-2."
                XC3100A-1 silicon is now available.

                Version:        Viewlogic Schematics - Revision 1.0 Rev E.

                Notes:This design is a clone of the Verilog files, which 
                largely document the design.

                Extraction:     At DOS prompt   pkunzip -d rev1e

Overview of file structure:

1. MOD_FPGA.
        Target          - 3 pages.
        Pci_bus         - 2 pages.
        Local_bus       - 2 pages.
        Time specs.

2. Target.
        Parity          - 1 page.
        Sram We regs    - 1 page.
        Ram Addr Cntr   - 1 page.
        Critpath        - 1 page.
        Arbiter         - 1 page.
        Pipcon          - 1 page
        Comparator      - 1 page.
        Addr Shift      - 1 page.

3. Pci_bus.
        SR_REG registers and bus data out.
        AD_REG registers and bus data in.
        Key PCI bus control signals.
        Pin location constraints for PCI bus and control signals.

4. Local_bus.
        SR_ADDR registerS and bus data out.
        AD_REG registers and bus data out.
        SR_REG register and bus data in.
        Key Local bus control signals.
        Pin location constraints for Local bus and control signals.


--------------------------------------------------------------------------
        R E V I S I O N         H I S T O R Y.

--------------------------------------------------------------------------

        April 14th:

        Verilog files for 3164A application.
        ------------------------------------

        Added LCA files for PCI_TOP, along with the original xnf files
        generated from the verilog.

        See \verilog and \verilog\xnf.

        REV1E.ZIP Viewlogic version of Verilog 3164A application note.
        --------------------------------------------------------------

        Fixed XSIMMAKE labeling errors for ram_cntr buses: Bus_A and Bus_B.
        The same problem was also fixed on IO buses, eg AD_REG was renamed
        AD__REG to avoid label expansion conflicts. This edit was made to
        both sets of buses: PCI and Local.

        Checked that Block types were Composite and not Module.




--------------------------------------------------------------------------
        R E V I S I O N         H I S T O R Y.
--------------------------------------------------------------------------



