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| XILINX APPLICATIONS XAPP007V:  TEST.00                     BN-4-20-94 |
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README file for the XC3000A Boundary-scan Emulator:
===================================================

Note: A more detailed description of this application can be found in 
Section 8 of the Xilinx Data Book.

TEST
----

This design file contains all the macros necessary to emulate IEEE 1149.1 
boundary scan as described in the application note "Boundary-scan Emulator 
for XC3000" (XAPP007). The design TEST provides a simple 4-pin example 
illustrating the use of the macros.

Design files included in directory TEST:

  README          This README file
  SCH\TEST.1      Top-level Viewlogic V4.1.3a schematic
  SCH\TAP_STAT.1  Schematic for TAP State Machine
  SCH\MISC_LOG.1  Schematic for Miscellaneous Logic
  SCH\IR.1        Schematic for Instruction Register
  SCH\BYPASSR.1   Schematic for Bypass Register
  SCH\DR.1        Schematic for sample Data Register
  SCH\DRINPUT.1   Schematic for DR Register Bit for an Input Pin
  SCH\DROUTPUT.1  Schematic for DR Register Bit for an Output Pin
  SCH\DRENHANC.1  Schematic for DR Register Bit for an Enhanced Output Pin
  SCH\DRENHBI.1   Schematic for DR Register Bit for an Enhanced Bidir Pin
  SYM\*.1         Viewlogic Symbols
  
  XNF\            Xilinx Netlists for High Level Schematic
  CPIP8H.CST      Placement constraints file
  CPIP8H.LCA      Placed and Routed LCA file
  CPIP8H.XRP      Xdelay timing report using XC3000A-6

Software Versions used:
  DS390 Version 4.1.3a Viewlogic and Interface


Implementation Notes:
  Other than locking pins to desired locations, the top-level schematic can be 
used as is. The remainder of the design-specific information is contained in 
the Data-Register macro, DR.
  The DR macro is created by cascading pad macros in the order desired, 
adding pads, and locking these pads to the corresponding pins. Usually, the 
separation of I/O buffers and pads onto different hierachical levels it not
recommended. Using Viewlogic, however, it has been shown to work in this 
situation, and is extremely convenient; it may not work with other schematic- 
capture programs. Additional macros must be included to control 3-state 
outputs.
  The CLBMAP in the DR macro is used to combine two update flip-flops from 
DRENHANC or DRENHBI macros. The use of CLBMAPs for this purpose is optional, 
but can save a significant number of CLBs in otherwise tight designs. One 
CLBMAP is required for each pair of flip-flops. To simplify routing the 
flip-flops combined should lie close to each other in the boundary-scan order.
Flip-flops from DRENHANC and DRENHBI macros can be combined in a CLBMAP.
  In the sample design, only the data-register pins were locked in place.
Typically, the TAP pins will also need to be locked down. If the LCA file for 
the sample design is viewed in XDE, test data enters the part at the TDI pin 
and is distributed through the Neon Blue net to the data, instruction and 
bypass registers. The data register bits are connected through the Hot Pink,
Lime Green, Red and Purple nets; there are two bits in CLB IB between the 
Lime Green and Red nets. The instruction register is connected through the 
Orange and Yellow nets, while the bypass register is connected through the 
White net. All test data exits via the Periwinkle net and the TDOUT pin.
