===============================================================================

 CELL NAME  : CDS_GEN_A2_OI2_OI (Z, A, B, C, D)

 INPUT      : A, B, C, D

 OUTPUT     : Z

 FUNCTION   : 2-INPUT AND and 2-INPUT NOR  into 2-INPUT NOR 

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_ADDR1 (S, CO, CI, A, B)

 INPUT      : CI, A, B

 OUTPUT     : S, CO

 FUNCTION   : 1 - BIT FULL ADDER 

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_AO3 (Z, A, B, C)

 INPUT      : A, B, C

 OUTPUT     : Z

 FUNCTION   : 3-INPUT AND-OR GATE 

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_AOI_1_2_2 (Z, A, B, C, D, E)

 INPUT      : A, B, C, D, E

 OUTPUT     : Z

 FUNCTION   : TWO 2-INPUT and ONE SINGLE INPUT AND into 3-INPUT NOR

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_AOI_1_2_3 (Z, A, B, C, D, E, F)

 INPUT      : A, B, C, D, E, F

 OUTPUT     : Z

 FUNCTION   : 1-INPUT, 2-INPUT and 3-INPUT AND into 3-INPUT NOR

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_AOI_2_2 (Z, A, B, C, D)

 INPUT      : A, B, C, D

 OUTPUT     : Z

 FUNCTION   : 2-WIDE 2-INPUT AND into 2-INPUT NOR 

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_AOI_2_2_2 (Z, A, B, C, D, E, F)

 INPUT      : A, B, C, D, E, F

 OUTPUT     : Z

 FUNCTION   : 3-WIDE 2-INPUT AND into 3-INPUT NOR

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_AOI_2_2_2_2 (Z, A, B, C, D, E, F, G, H)

 INPUT      : A, B, C, D, E, F, G, H

 OUTPUT     : Z

 FUNCTION   : 4-WIDE 2-INPUT AND into 4-INPUT NOR

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_AOI_2_3 (Z, A, B, C, D, E)

 INPUT      : A, B, C, D, E

 OUTPUT     : Z

 FUNCTION   : 2-INPUT AND and 3-INPUT AND into 2-INPUT NOR   

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_AOI_3 (Z, A, B, C)

 INPUT      : A, B, C

 OUTPUT     : Z

 FUNCTION   : 3-INPUT AND-OR INVERT GATE 

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_AOI_3_3 (Z, A, B, C, D, E, F)

 INPUT      : A, B, C, D, E, F

 OUTPUT     : Z

 FUNCTION   : 2-WIDE 3-INPUT AND into 2-INPUT NOR 

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_AO_2_2 (Z, A, B, C, D)

 INPUT      : A, B, C, D

 OUTPUT     : Z

 FUNCTION   : 2-WIDE 2-INPUT AND into 2-INPUT OR

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_AO_2_2_2 (Z, A, B, C, D, E, F)

 INPUT      : A, B, C, D, E, F

 OUTPUT     : Z

 FUNCTION   : 3-WIDE 2-INPUT AND into 3-INPUT OR

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_AO_2_2_2_2 (Z, A, B, C, D, E, F, G, H)

 INPUT      : A, B, C, D, E, F, G, H

 OUTPUT     : Z

 FUNCTION   : 4-WIDE 2-INPUT AND into 4-INPUT OR

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_AO_2_3 (Z, A, B, C, D, E)

 INPUT      : A, B, C, D, E

 OUTPUT     : Z

 FUNCTION   : 2-INPUT AND and 3-INPUT AND into 2-INPUT OR   

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_AO_3 (Z, A, B, C)

 INPUT      : A, B, C

 OUTPUT     : Z

 FUNCTION   : 3-INPUT AND-OR GATE 

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_AO_3_3 (Z, A, B, C, D, E, F)

 INPUT      : A, B, C, D, E, F

 OUTPUT     : Z

 FUNCTION   : 2-WIDE 3-INPUT AND into 2-INPUT OR 

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_AXO_2_2 (Z, A, B, C, D)

 INPUT      : A, B, C, D

 OUTPUT     : Z

 FUNCTION   : 2-WIDE 2-INPUT AND into 2-INPUT XOR 

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_AXO_2_3 (Z, A, B, C, D, E)

 INPUT      : A, B, C, D, E

 OUTPUT     : Z

 FUNCTION   : 2-INPUT AND and 3-INPUT AND into 2-INPUT XOR   

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_AXO_2_4 (Z, A, B, C, D, E, F)

 INPUT      : A, B, C, D, E, F

 OUTPUT     : Z

 FUNCTION   : 2-INPUT AND and 4-INPUT AND into 2-INPUT XOR   

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_BUF_BD (ZI, PO, A, EN, TN, PI, IO)

 INPUT      : A, EN, TN, PI

 OUTPUT     : ZI, PO

 FUNCTION   : BI-DIRCTIONAL BUFFER WITH TEST INPUTS .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_BUF_BD_I (ZI, PO, A, EN, TN, PI, IO)

 INPUT      : A, EN, TN, PI

 OUTPUT     : ZI, PO

 FUNCTION   : BI-DIRCTIONAL BUFFER  WITH INVERTED OUTPUT

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_BUF_BD_OD (ZI, PO, EN, TN, PI, IO)

 INPUT      : EN, TN, PI

 OUTPUT     : ZI, PO

 FUNCTION   : BI-DIRCTIONAL BUFFER  WITH OPEN DRAIN 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_BUF_BD_OD_I (ZI, PO, EN, TN, PI, IO)

 INPUT      : EN, TN, PI

 OUTPUT     : ZI, PO

 FUNCTION   : BI-DIRCTIONAL BUFFER  WITH OPEN DRAIN 
              AND INVERTED OUTPUT

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_BUF_BD_OS (ZI, PO, E, TN, PI, IO)

 INPUT      : E, TN, PI

 OUTPUT     : ZI, PO

 FUNCTION   : BI-DIRCTIONAL BUFFER  WITH OPEN SOURCE  

 MODEL TYPE : GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_BUF_BD_OS_I (ZI, PO, E, TN, PI, IO)

 INPUT      : E, TN, PI

 OUTPUT     : ZI, PO

 FUNCTION   : BI-DIRCTIONAL BUFFER  WITH OPEN SOURCE  
              AND INVERTED OUPUT 

 MODEL TYPE : GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_BUF_BD_PD (ZI, PO, A, EN, TN, PI, IO)

 INPUT      : A, EN, TN, PI

 OUTPUT     : ZI, PO

 FUNCTION   : BI-DIRCTIONAL BUFFER  WITH PULL DOWN 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_BUF_BD_PD_I (ZI, PO, A, EN, TN, PI, IO)

 INPUT      : A, EN, TN, PI

 OUTPUT     : ZI, PO

 FUNCTION   : BI-DIRCTIONAL BUFFER  WITH PULL DOWN 
              AND INVERTED OUPUT .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_BUF_BD_PU (ZI, PO, A, EN, TN, PI, IO)

 INPUT      : A, EN, TN, PI

 OUTPUT     : ZI, PO

 FUNCTION   : BI-DIRCTIONAL BUFFER  WITH PULL UP

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_BUF_BD_PU_I (ZI, PO, A, EN, TN, PI, IO)

 INPUT      : A, EN, TN, PI

 OUTPUT     : ZI, PO

 FUNCTION   : BI-DIRCTIONAL BUFFER  WITH PULL UP
              AND INVERTED OUPUT .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_BUF_TRI (Z, A, EN, TN)

 INPUT      : A, EN, TN

 OUTPUT     : Z

 FUNCTION   : THREE STATE OUTPUT BUFFER 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_BUF_TRI_OD (Z, EN, TN)

 INPUT      : EN, TN

 OUTPUT     : Z

 FUNCTION   : THREE STATE OUTPUT BUFFER WITH OPEN DRAIN

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_BUF_TRI_OS (Z, E, TN)

 INPUT      : E, TN

 OUTPUT     : Z

 FUNCTION   : THREE STATE OUTPUT BUFFER WITH OPEN SOURCE

 MODEL TYPE : GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_BUF_UNI (Z, A)

 INPUT      : A

 OUTPUT     : Z

 FUNCTION   : UNIDIRECT OUTPUT BUFFER

 MODEL TYPE : GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_DECOD_2X4 (Z0, Z1, Z2, Z3, A, B)

 INPUT      : A, B

 OUTPUT     : Z0, Z1, Z2, Z3

 FUNCTION   : TWO TO FOUR DECODER

 MODEL TYPE : GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_DECOD_G_2X4 (Z0, Z1, Z2, Z3, A, B, G)

 INPUT      : A, B, G

 OUTPUT     : Z0, Z1, Z2, Z3

 FUNCTION   : TWO TO FOUR DECODER WITH ACTVE HIGH GATE INPUT

 MODEL TYPE : GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_DIFF_BUF (Y, YN, A, AN)

 INPUT      : A, AN

 OUTPUT     : Y, YN

 FUNCTION   : BUFFER WITH DIFFERENTIAL INPUT AND OUTPUT

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_DUAL_INV (Y, Z, A)

 INPUT      : A

 OUTPUT     : Y, Z

 FUNCTION   : INVERTER INTO INVERTER

 MODEL TYPE : GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_LD_P_RB_SB (Q, QN, SEL, D, SI, CP, RB, SB)

 INPUT      : SEL, D, SI, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : D-TYPE FLIP-FLOP AND A D-TYPE LATCH WITH  
              ASYNCHRONOUS CLEAR and PRESET ( ACTIVE LOW ) .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_LD_P_RB_SB_NO (Q, QN, SEL, D, SI, CP, RB, SB)

 INPUT      : SEL, D, SI, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : D-TYPE FLIP-FLOP AND A D-TYPE LATCH WITH  
              ASYNCHRONOUS CLEAR and PRESET ( ACTIVE LOW ) .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N (Q, QN, D, CP)

 INPUT      : D, CP

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_CEB_NO (Q, QN, D, CP, CEB)

 INPUT      : D, CP, CEB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW CLOCK 
              ENABLE 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_CEB_S_NO (Q, QN, D, CEB, CP, S)

 INPUT      : D, CEB, CP, S

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP FLOP WITH ACTIVE LOW ENABLE
              AND ACTIVE HIGH ASYNCHRONOUS PRESET.
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_CE_NO (Q, QN, D, CP, CE)

 INPUT      : D, CP, CE

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH CLOCK 
              ENABLE 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_CE_RB_NO(Q, QN, D, CP, CE, RB)

 INPUT      : D, CP, CE, RB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH CLOCK 
              ENABLE AND ACTIVE LOW ASYNCHRONOUS RESET

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_CE_RB_SB_X_NO (Q, QN, D, CE, RB, SB, CP)

 INPUT      : D, CE, RB, SB, CP

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP FLOP WITH ACTIVE HIGH ENABLE
              AND ACTIVE LOW ASYNCHRONOUS SET AND RESET.
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_CE_S_NO (Q, QN, D, CE, CP, S)

 INPUT      : D, CE, CP, S

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP FLOP WITH ACTIVE HIGH ENABLE
              AND ACTIVE HIGH ASYNCHRONOUS SET.
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_NO (Q, QN, D, CP)

 INPUT      : D, CP

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_RB_NO (Q, QN, D, CP, RB)

 INPUT      : D, CP, RB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS CLEAR 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_RB_SB (Q, QN, D, CP, RB, SB)

 INPUT      : D, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET AND CLEAR .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_RB_SB_NO (Q, QN, D, CP, RB, SB)

 INPUT      : D, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET AND CLEAR .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_RB_SB_X (Q, QN, D, CP, RB, SB)

 INPUT      : D, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET AND CLEAR . ILLEGAL OUPUT WHEN BOTH
              SET AND CLEAR ARE LOW .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_RB_SB_X_NO (Q, QN, D, CP, RB, SB)

 INPUT      : D, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET AND CLEAR . ILLEGAL OUPUT WHEN BOTH
              SET AND CLEAR ARE LOW .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_R_NO (Q, QN, D, CP, R)

 INPUT      : D, CP, R

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH
              ASYNCHRONOUS CLEAR 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_R_S (Q, QN, D, CP, R, S)

 INPUT      : D, CP, R, S

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH
              ASYNCHRONOUS SET AND CLEAR .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_R_S_NO (Q, QN, D, CP, R, S)

 INPUT      : D, CP, R, S

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH
              ASYNCHRONOUS SET AND CLEAR .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_R_S_X (Q, QN, D, CP, R, S)

 INPUT      : D, CP, R, S

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH
              ASYNCHRONOUS SET AND CLEAR .ILLEGAL OUTPUT OCCURS WHEN
              BOTH SET AND CLEAR ARE ACTIVE .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_R_S_X_NO (Q, QN, D, CP, R, S)

 INPUT      : D, CP, R, S

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH
              ASYNCHRONOUS SET AND CLEAR .ILLEGAL OUTPUT OCCURS WHEN
              BOTH SET AND CLEAR ARE ACTIVE .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_SB_NO (Q, QN, D, CP, SB)

 INPUT      : D, CP, SB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_SB_RB (Q, QN, D, CP, RB, SB)

 INPUT      : D, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET AND CLEAR .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_SB_RB_NO (Q, QN, D, CP, RB, SB)

 INPUT      : D, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET AND CLEAR .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_SD (Q, QN, D, CP, TI, TE)

 INPUT      : D, CP, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP WITH SCAN INPUTS 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_SD_NO (Q, QN, D, CP, TI, TE)

 INPUT      : D, CP, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP WITH SCAN INPUTS 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_SD_RB_NO (Q, QN, D, CP, RB, TI, TE)

 INPUT      : D, CP, RB, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS RESET WITH  SCAN INPUTS 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_SD_RB_SB (Q, QN, D, CP, RB, SB, TI, TE)

 INPUT      : D, CP, RB, SB, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS CLEAR AND SET,  AND WITH  SCAN INPUTS 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_SD_RB_SB_NO (Q, QN, D, CP, RB, SB, TI, TE)

 INPUT      : D, CP, RB, SB, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS CLEAR AND SET,  AND WITH  SCAN INPUTS 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_SD_R_NO (Q, QN, D, CP, R, TI, TE)

 INPUT      : D, CP, R, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP WITH SCAN INPUTS
              AND ACTIVE HIGH ASYNCHRONOUS CLEAR 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_SD_SB_NO (Q, QN, D, CP, SB, TI, TE)

 INPUT      : D, CP, SB, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET WITH  SCAN INPUTS 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_SD_S_NO (Q, QN, D, CP, S, TI, TE)

 INPUT      : D, CP, S, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET WITH  SCAN INPUTS 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_S_NO (Q, QN, D, CP, S)

 INPUT      : D, CP, S

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH
              ASYNCHRONOUS SET 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_S_R (Q, QN, D, CP, S, R)

 INPUT      : D, CP, S, R

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH
              ASYNCHRONOUS SET AND CLEAR .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_N_S_R_NO (Q, QN, D, CP, S, R)

 INPUT      : D, CP, S, R

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH
              ASYNCHRONOUS SET AND CLEAR .                       
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P (Q, QN, D, CP)

 INPUT      : D, CP

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_CEB_NO (Q, QN, D, CP, CEB)

 INPUT      : D, CP, CEB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW CLOCK 
              ENABLE 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_CEB_S_NO (Q, QN, D, CEB, CP, S)

 INPUT      : D, CEB, CP, S

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP FLOP WITH ACTIVE LOW ENABLE
              AND ACTIVE HIGH ASYNCHRONOUS SET.
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_CE_NO (Q, QN, D, CP, CE)

 INPUT      : D, CP, CE

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH CLOCK 
              ENABLE 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_CE_RB_NO(Q, QN, D, CP, CE, RB)

 INPUT      : D, CP, CE, RB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH CLOCK 
              ENABLE AND ACTIVE LOW ASYNCHRONOUS RESET

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_CE_RB_SB_X_NO (Q, QN, D, CE, RB, SB, CP)

 INPUT      : D, CE, RB, SB, CP

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP FLOP WITH ACTIVE HIGH ENABLE
              AND ACTIVE LOW ASYNCHRONOUS SET AND RESET.
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_CE_S_NO (Q, QN, D, CE, CP, S)

 INPUT      : D, CE, CP, S

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP FLOP WITH ACTIVE HIGH ENABLE
              AND ACTIVE HIGH ASYNCHRONOUS SET.
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_NO (Q, QN, D, CP)

 INPUT      : D, CP

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_PLD (Q, QN, D, CP, PD, PLD)

 INPUT      : D, CP, PD, PLD

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH PARALLEL LOAD. 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_PLD_NO (Q, QN, D, CP, PD, PLD)

 INPUT      : D, CP, PD, PLD

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH PARALLEL LOAD. 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_R (Q, QN, D, CP, R)

 INPUT      : D, CP, R

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH
              ASYNCHRONOUS CLEAR 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_RB (Q, QN, D, CP, RB)

 INPUT      : D, CP, RB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS CLEAR 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_RBC (Q, QN, D, CP, RBC)

 INPUT      : D, CP, RBC

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              SYNCHRONOUS CLEAR

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_RBC_LD (Q, QN, D, CP, RBC, LD)

 INPUT      : D, CP, RBC, LD

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              SYNCHRONOUS CLEAR AND LOAD

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_RBC_LD_NO (Q, QN, D, CP, RBC, LD)

 INPUT      : D, CP, RBC, LD

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              SYNCHRONOUS CLEAR AND LOAD      
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_RBC_NO (Q, QN, D, CP, RBC)

 INPUT      : D, CP, RBC

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              SYNCHRONOUS CLEAR      
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_RB_NO (Q, QN, D, CP, RB)

 INPUT      : D, CP, RB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS CLEAR 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_RB_PLD (Q, QN, D, CP, PD, PLD, RB)

 INPUT      : D, CP, PD, PLD, RB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS CLEAR AND PARALLEL LOAD .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_RB_PLD_NO (Q, QN, D, CP, PD, PLD, RB)

 INPUT      : D, CP, PD, PLD, RB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS CLEAR AND PARALLEL LOAD .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_RB_SB (Q, QN, D, CP, RB, SB)

 INPUT      : D, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET AND CLEAR .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_RB_SB_NO (Q, QN, D, CP, RB, SB)

 INPUT      : D, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET AND CLEAR .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_RB_SB_X (Q, QN, D, CP, RB, SB)

 INPUT      : D, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET AND CLEAR . ILLEGAL OUPUT WHEN BOTH
              SET AND CLEAR ARE LOW .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_RB_SB_X_NO (Q, QN, D, CP, RB, SB)

 INPUT      : D, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET AND CLEAR . ILLEGAL OUPUT WHEN BOTH
              SET AND CLEAR ARE LOW .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_R_NO (Q, QN, D, CP, R)

 INPUT      : D, CP, R

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH
              ASYNCHRONOUS CLEAR 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_R_PLD (Q, QN, D, CP, PD, PLD, R)

 INPUT      : D, CP, PD, PLD, R

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH
              ASYNCHRONOUS RESET AND PARALLEL LOAD .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_R_PLD_NO (Q, QN, D, CP, PD, PLD, R)

 INPUT      : D, CP, PD, PLD, R

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH
              ASYNCHRONOUS RESET AND PARALLEL LOAD .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_R_S (Q, QN, D, CP, R, S)

 INPUT      : D, CP, R, S

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH
              ASYNCHRONOUS SET AND CLEAR .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_R_S_NO (Q, QN, D, CP, R, S)

 INPUT      : D, CP, R, S

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH
              ASYNCHRONOUS SET AND CLEAR .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_R_S_X (Q, QN, D, CP, R, S)

 INPUT      : D, CP, R, S

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH
              ASYNCHRONOUS SET AND CLEAR .ILLEGAL OUTPUT OCCURS WHEN
              BOTH SET AND CLEAR ARE ACTIVE .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_R_S_X_NO (Q, QN, D, CP, R, S)

 INPUT      : D, CP, R, S

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH
              ASYNCHRONOUS SET AND CLEAR .ILLEGAL OUTPUT OCCURS WHEN
              BOTH SET AND CLEAR ARE ACTIVE .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_SB (Q, QN, D, CP, SB)

 INPUT      : D, CP, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_SB_NO (Q, QN, D, CP, SB)

 INPUT      : D, CP, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_SB_PLD (Q, QN, D, CP, PD, PLD, SB)

 INPUT      : D, CP, PD, PLD, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET AND PARALLEL LOAD .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_SB_PLD_NO (Q, QN, D, CP, PD, PLD, SB)

 INPUT      : D, CP, PD, PLD, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET AND PARALLEL LOAD .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_SB_RB (Q, QN, D, CP, RB, SB)

 INPUT      : D, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET AND CLEAR .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_SB_RB_NO (Q, QN, D, CP, RB, SB)

 INPUT      : D, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET AND CLEAR .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_SD (Q, QN, D, CP, TI, TE)

 INPUT      : D, CP, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH SCAN INPUTS 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_SD_NO (Q, QN, D, CP, TI, TE)

 INPUT      : D, CP, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH SCAN INPUTS 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_SD_RB (Q, QN, D, CP, RB, TI, TE)

 INPUT      : D, CP, RB, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH SCAN INPUTS AND
              ACTIVE LOW ASYNCHRONOUS CLEAR 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_SD_RB_NO (Q, QN, D, CP, RB, TI, TE)

 INPUT      : D, CP, RB, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH SCAN INPUTS
              AND ACTIVE LOW ASYNCHRONOUS CLEAR 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_SD_RB_SB (Q, QN, D, CP, RB, SB, TI, TE)

 INPUT      : D, CP, RB, SB, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS CLEAR AND SET,  AND WITH  SCAN INPUTS 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_SD_RB_SB_NO (Q, QN, D, CP, RB, SB, TI, TE)

 INPUT      : D, CP, RB, SB, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS CLEAR AND SET,  AND WITH  SCAN INPUTS 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_SD_R_NO (Q, QN, D, CP, R, TI, TE)

 INPUT      : D, CP, R, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH SCAN INPUTS
              AND ACTIVE HIGH ASYNCHRONOUS CLEAR 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_SD_SB (Q, QN, D, CP, SB, TI, TE)

 INPUT      : D, CP, SB, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET WITH  SCAN INPUTS 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_SD_SB_NO (Q, QN, D, CP, SB, TI, TE)

 INPUT      : D, CP, SB, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET WITH  SCAN INPUTS 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_SD_S_NO (Q, QN, D, CP, S, TI, TE)

 INPUT      : D, CP, S, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH
              ASYNCHRONOUS SET WITH  SCAN INPUTS 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_S_NO (Q, QN, D, CP, S)

 INPUT      : D, CP, S

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH
              ASYNCHRONOUS SET 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_S_PLD (Q, QN, D, CP, PD, PLD, S)

 INPUT      : D, CP, PD, PLD, S

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH
              ASYNCHRONOUS SET AND PARALLEL LOAD ( ACTIVE LOW ) .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_S_PLD_NO (Q, QN, D, CP, PD, PLD, S)

 INPUT      : D, CP, PD, PLD, S

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH
              ASYNCHRONOUS SET AND PARALLEL LOAD ( ACTIVE LOW ).
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_S_R (Q, QN, D, CP, S, R)

 INPUT      : D, CP, S, R

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH
              ASYNCHRONOUS SET AND CLEAR .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FD_P_S_R_NO (Q, QN, D, CP, S, R)

 INPUT      : D, CP, S, R

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH
              ASYNCHRONOUS SET AND CLEAR .                       
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJKB_N_NO (Q, QN, J, K, CP)

 INPUT      : J, K, CP

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED JK_ FLIP FLOP  

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJKB_N_RB_NO (Q, QN, J, K, CP, RB)

 INPUT      : J, K, CP, RB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED JK_ FLIP FLOP, WITH ACTIVE LOW
              ASYNCHRONOUS CLEAR.

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJKB_N_RB_SB_X_NO (Q, QN, J, K, CP, SB, RB)

 INPUT      : J, K, CP, SB, RB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED JK_ FLIP FLOP, WITH ACTIVE LOW
              ASYNCHRONOUS CLEAR AND SBSET . ILLEGAL OUTPUT OCCURS WHEN BOTH
              SBSET AND CLEAR ARE ACTIVE

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJKB_N_R_NO (Q, QN, J, K, CP, R)

 INPUT      : J, K, CP, R

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED JK_ FLIP FLOP, WITH ACTIVE HIGH
              ASYNCHRONOUS CLEAR.

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJKB_N_SB_NO (Q, QN, J, K, CP, SB)

 INPUT      : J, K, CP, SB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED JK_ FLIP FLOP, WITH ACTIVE LOW
              ASYNCHRONOUS SBSET. 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJKB_N_S_NO (Q, QN, J, K, CP, S)

 INPUT      : J, K, CP, S

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED JK_ FLIP FLOP, WITH ACTIVE HIGH
              ASYNCHRONOUS SSET.

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJKB_P_NO (Q, QN, J, K, CP)

 INPUT      : J, K, CP

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED JK_ FLIP FLOP

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJKB_P_RB_NO (Q, QN, J, K, CP, RB)

 INPUT      : J, K, CP, RB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED JK_ FLIP FLOP, WITH ASYNCHRONOUS CLEAR
              ACTIVE LOW

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJKB_P_RB_SB_X_NO (Q, QN, J, K, SB, RB, CP)

 INPUT      : J, K, SB, RB, CP

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED JK_ FLIP FLOP, WITH ACTIVE LOW
              ASYNCHRONOUS CLEAR AND SBSET. ILLEGAL OUTPUT OCCURS WHEN BOTH
              SBSET AND CLEAR ARE ACTIVE

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJKB_P_R_NO (Q, QN, J, K, CP, R)

 INPUT      : J, K, CP, R

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED JK_ FLIP FLOP, WITH ASYNCHRONOUS CLEAR
              ACTIVE HIGH

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJKB_P_SB_NO (Q, QN, J, K, CP, SB)

 INPUT      : J, K, CP, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED JK_ FLIP FLOP, WITH ASYNCHRONOUS SET
              ACTIVE LOW

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJKB_P_S_NO (Q, QN, J, K, CP, S)

 INPUT      : J, K, CP, S

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED JK_ FLIP FLOP, WITH ASYNCHRONOUS SET
              ACTIVE HIGH

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_N (Q, QN, J, K, CP)

 INPUT      : J, K, CP

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED JK FLIP FLOP  

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_N_NO (Q, QN, J, K, CP)

 INPUT      : J, K, CP

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED JK FLIP FLOP  
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_N_RB_SB (Q, QN, J, K, CP, RB, SB)

 INPUT      : J, K, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED JK FLIP FLOP, WITH ACTIVE LOW 
              ASYNCHRONOUS CLEAR AND PRESET .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_N_RB_SB_NO (Q, QN, J, K, CP, RB, SB)

 INPUT      : J, K, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED JK FLIP FLOP, WITH ACTIVE LOW 
              ASYNCHRONOUS CLEAR AND PRESET .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_N_RB_SB_X (Q, QN, J, K, CP, RB, SB)

 INPUT      : J, K, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED JK FLIP FLOP, WITH ACTIVE LOW 
              ASYNCHRONOUS CLEAR AND PRESET . ILLEGAL OUTPUT OCCURS WHEN BOTH
              PRESET AND CLEAR ARE ACTIVE 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_N_RB_SB_X_NO (Q, QN, J, K, CP, RB, SB)

 INPUT      : J, K, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED JK FLIP FLOP, WITH ACTIVE LOW 
              ASYNCHRONOUS CLEAR AND PRESET . ILLEGAL OUTPUT OCCURS WHEN BOTH
              PRESET AND CLEAR ARE ACTIVE 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_N_SB_RB (Q, QN, J, K, CP, RB, SB)

 INPUT      : J, K, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED JK FLIP FLOP, WITH ACTIVE LOW 
              ASYNCHRONOUS CLEAR AND PRESET .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_N_SB_RB_NO (Q, QN, J, K, CP, RB, SB)

 INPUT      : J, K, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED JK FLIP FLOP, WITH ACTIVE LOW 
              ASYNCHRONOUS CLEAR AND PRESET .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_N_SD (Q, QN, J, K, CP, TI, TE)

 INPUT      : J, K, CP, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED J-K FLIP FLOP WITH SCAN INPUTS 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_N_SD_NO (Q, QN, J, K, CP, TI, TE)

 INPUT      : J, K, CP, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED J-K FLIP FLOP WITH SCAN INPUTS 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_N_SD_RB_SB (Q, QN, J, K, CP, RB, SB, TI, TE)

 INPUT      : J, K, CP, RB, SB, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED J-K FLIP FLOP WITH SCAN INPUTS 
              WITH ASYNCHRONOUS CLEAR AND SET ACTIVE LOW 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_N_SD_RB_SB_NO (Q, QN, J, K, CP, RB, SB, TI, TE)

 INPUT      : J, K, CP, RB, SB, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED J-K FLIP FLOP WITH SCAN INPUTS 
              WITH ASYNCHRONOUS CLEAR AND SET ACTIVE LOW 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_N_S_R (Q, QN, J, K, CP, R, S)

 INPUT      : J, K, CP, R, S

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED JK FLIP FLOP, WITH ACTIVE HIGH
              ASYNCHRONOUS CLEAR AND PRESET .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_N_S_R_NO (Q, QN, J, K, CP, R, S)

 INPUT      : J, K, CP, R, S

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED JK FLIP FLOP, WITH ACTIVE HIGH
              ASYNCHRONOUS CLEAR AND PRESET .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_P (Q, QN, J, K, CP)

 INPUT      : J, K, CP

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED JK FLIP FLOP  

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_P_NO (Q, QN, J, K, CP)

 INPUT      : J, K, CP

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED JK FLIP FLOP  
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_P_R (Q, QN, J, K, CP, R)

 INPUT      : J, K, CP, R

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED JK FLIP FLOP, WITH ASYNCHRONOUS CLEAR 
              ACTIVE HIGH   

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_P_RB (Q, QN, J, K, CP, RB)

 INPUT      : J, K, CP, RB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED JK FLIP FLOP, WITH ASYNCHRONOUS CLEAR 
              ACTIVE LOW   

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_P_RB_NO (Q, QN, J, K, CP, RB)

 INPUT      : J, K, CP, RB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED JK FLIP FLOP, WITH ASYNCHRONOUS CLEAR 
              ACTIVE LOW   
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_P_RB_SB (Q, QN, J, K, CP, RB, SB)

 INPUT      : J, K, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED JK FLIP FLOP, WITH ACTIVE LOW 
              ASYNCHRONOUS CLEAR AND PRESET .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_P_RB_SB_NO (Q, QN, J, K, CP, RB, SB)

 INPUT      : J, K, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED JK FLIP FLOP, WITH ACTIVE LOW 
              ASYNCHRONOUS CLEAR AND PRESET .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_P_RB_SB_X (Q, QN, J, K, CP, RB, SB)

 INPUT      : J, K, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED JK FLIP FLOP, WITH ACTIVE LOW 
              ASYNCHRONOUS CLEAR AND PRESET . ILLEGAL OUTPUT OCCURS WHEN BOTH
              PRESET AND CLEAR ARE ACTIVE 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_P_RB_SB_X_NO (Q, QN, J, K, CP, RB, SB)

 INPUT      : J, K, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED JK FLIP FLOP, WITH ACTIVE LOW 
              ASYNCHRONOUS CLEAR AND PRESET . ILLEGAL OUTPUT OCCURS WHEN BOTH
              PRESET AND CLEAR ARE ACTIVE 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_P_R_NO (Q, QN, J, K, CP, R)

 INPUT      : J, K, CP, R

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED JK FLIP FLOP, WITH ASYNCHRONOUS CLEAR 
              ACTIVE HIGH   
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_P_S (Q, QN, J, K, CP, S)

 INPUT      : J, K, CP, S

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED JK FLIP FLOP, WITH ASYNCHRONOUS SET 
              ACTIVE HIGH   

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_P_SB (Q, QN, J, K, CP, SB)

 INPUT      : J, K, CP, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED JK FLIP FLOP, WITH ASYNCHRONOUS SET 
              ACTIVE LOW  

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_P_SB_NO (Q, QN, J, K, CP, SB)

 INPUT      : J, K, CP, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED JK FLIP FLOP, WITH ASYNCHRONOUS SET 
              ACTIVE LOW   
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_P_SB_RB (Q, QN, J, K, CP, RB, SB)

 INPUT      : J, K, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED JK FLIP FLOP, WITH ACTIVE LOW 
              ASYNCHRONOUS CLEAR AND PRESET .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_P_SB_RB_NO (Q, QN, J, K, CP, RB, SB)

 INPUT      : J, K, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED JK FLIP FLOP, WITH ACTIVE LOW 
              ASYNCHRONOUS CLEAR AND PRESET .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_P_SD (Q, QN, J, K, CP, TI, TE)

 INPUT      : J, K, CP, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED J-K FLIP FLOP WITH SCAN INPUTS 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_P_SD_NO (Q, QN, J, K, CP, TI, TE)

 INPUT      : J, K, CP, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED J-K FLIP FLOP WITH SCAN INPUTS 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_P_SD_RB (Q, QN, J, K, CP, RB, TI, TE)

 INPUT      : J, K, CP, RB, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED J-K FLIP FLOP WITH SCAN INPUTS 
              AND ASYNCHRONOUS CLEAR ACTIVE LOW 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_P_SD_RB_NO (Q, QN, J, K, CP, RB, TI, TE)

 INPUT      : J, K, CP, RB, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED J-K FLIP FLOP WITH SCAN INPUTS 
              AND ASYNCHRONOUS CLEAR ACTIVE LOW 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_P_SD_RB_SB (Q, QN, J, K, CP, RB, SB, TI, TE)

 INPUT      : J, K, CP, RB, SB, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED J-K FLIP FLOP WITH SCAN INPUTS 
              WITH ASYNCHRONOUS CLEAR AND SET ACTIVE LOW 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_P_SD_RB_SB_NO (Q, QN, J, K, CP, RB, SB, TI, TE)

 INPUT      : J, K, CP, RB, SB, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED J-K FLIP FLOP WITH SCAN INPUTS 
              WITH ASYNCHRONOUS CLEAR AND SET ACTIVE LOW 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_P_SD_SB (Q, QN, J, K, CP, SB, TI, TE)

 INPUT      : J, K, CP, SB, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED J-K FLIP FLOP WITH SCAN INPUTS 
              AND ASYNCHRONOUS SET ACTIVE LOW 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_P_SD_SB_NO (Q, QN, J, K, CP, SB, TI, TE)

 INPUT      : J, K, CP, SB, TI, TE

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED J-K FLIP FLOP WITH SCAN INPUTS 
              AND ASYNCHRONOUS SET ACTIVE LOW 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_P_S_NO (Q, QN, J, K, CP, S)

 INPUT      : J, K, CP, S

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED JK FLIP FLOP, WITH ASYNCHRONOUS SET 
              ACTIVE HIGH 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_P_S_R (Q, QN, J, K, CP, R, S)

 INPUT      : J, K, CP, R, S

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED JK FLIP FLOP, WITH ACTIVE HIGH
              ASYNCHRONOUS CLEAR AND PRESET .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FJK_P_S_R_NO (Q, QN, J, K, CP, R, S)

 INPUT      : J, K, CP, R, S

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED JK FLIP FLOP, WITH ACTIVE HIGH
              ASYNCHRONOUS CLEAR AND PRESET .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FRS_N (Q, QN, S, R, CP)

 INPUT      : S, R, CP

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED R-S FLIP-FLOP

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FRS_N_NO (Q, QN, S, R, CP)

 INPUT      : S, R, CP

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED R-S FLIP-FLOP
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FRS_N_RB_SB (Q, QN, S, R, CP, RB, SB)

 INPUT      : S, R, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED R-S FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET AND  RESET 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FRS_N_RB_SB_NO (Q, QN, S, R, CP, RB, SB)

 INPUT      : S, R, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED R-S FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET AND  RESET .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FRS_N_SB_RB_X (Q, QN, S, R, CP, RB, SB)

 INPUT      : S, R, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED R-S FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET AND  RESET . ILLEGAL OUTPUT OCCURS WHEN 
              BOTH SET AND RESET ARE ACTIVE .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FRS_N_SB_RB_X_NO (Q, QN, S, R, CP, RB, SB)

 INPUT      : S, R, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED R-S FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET AND  RESET 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FRS_N_S_R_X (Q, QN, S, R, CP, RESET, SET)

 INPUT      : S, R, CP, RESET, SET

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED R-S FLIP-FLOP WITH ACTIVE HIGH
              ASYNCHRONOUS SET AND  RESET . ILLEGAL OUTPUT OCCURS WHEN
              BOTH SET AND RESET ARE ACTIVE .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FRS_N_S_R_X_NO (Q, QN, S, R, CP, RESET, SET)

 INPUT      : S, R, CP, RESET, SET

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED R-S FLIP-FLOP WITH ACTIVE HIGH
              ASYNCHRONOUS SET AND  RESET ILLEGAL OUTPUT OCCURS WHEN
              BOTH SET AND RESET ARE ACTIVE .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FRS_P (Q, QN, S, R, CP)

 INPUT      : S, R, CP

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED R-S FLIP-FLOP

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FRS_P_NO (Q, QN, S, R, CP)

 INPUT      : S, R, CP

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED R-S FLIP-FLOP
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FRS_P_RB_SB (Q, QN, S, R, CP, RB, SB)

 INPUT      : S, R, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED R-S FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET AND  RESET 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FRS_P_RB_SB_NO (Q, QN, S, R, CP, RB, SB)

 INPUT      : S, R, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED R-S FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET AND  RESET .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FRS_P_SB_RB_X (Q, QN, S, R, CP, RB, SB)

 INPUT      : S, R, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED R-S FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET AND  RESET . ILLEGAL OUTPUT OCCURS WHEN 
              BOTH SET AND RESET ARE ACTIVE .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FRS_P_SB_RB_X_NO (Q, QN, S, R, CP, RB, SB)

 INPUT      : S, R, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED R-S FLIP-FLOP WITH ACTIVE LOW
              ASYNCHRONOUS SET AND  RESET 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FRS_P_S_R_X (Q, QN, S, R, CP, RESET, SET)

 INPUT      : S, R, CP, RESET, SET

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED R-S FLIP-FLOP WITH ACTIVE HIGH
              ASYNCHRONOUS SET AND  RESET . ILLEGAL OUTPUT OCCURS WHEN
              BOTH SET AND RESET ARE ACTIVE .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FRS_P_S_R_X_NO (Q, QN, S, R, CP, RESET, SET)

 INPUT      : S, R, CP, RESET, SET

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED R-S FLIP-FLOP WITH ACTIVE HIGH
              ASYNCHRONOUS SET AND  RESET ILLEGAL OUTPUT OCCURS WHEN
              BOTH SET AND RESET ARE ACTIVE .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FSR_N (Q, QN, S, R, CP)

 INPUT      : S, R, CP

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED R-S FLIP-FLOP

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FSR_N_NO (Q, QN, S, R, CP)

 INPUT      : S, R, CP

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED R-S FLIP-FLOP
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FSR_P (Q, QN, S, R, CP)

 INPUT      : S, R, CP

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED R-S FLIP-FLOP

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FSR_P_NO (Q, QN, S, R, CP)

 INPUT      : S, R, CP

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED R-S FLIP-FLOP
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_N_RB_SB (Q, QN, CP, RB, SB)

 INPUT      : CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED TOGGLE FLIP FLOP WITH ACTIVE LOW
              ASYNCHRONOUS CLEAR AND PRESET

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_N_RB_SB_NO (Q, QN, CP, RB, SB)

 INPUT      : CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED TOGGLE FLIP FLOP WITH ACTIVE LOW
              ASYNCHRONOUS CLEAR AND PRESET
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_N_RB_SB_X (Q, QN, CP, RB, SB)

 INPUT      : CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED TOGGLE FLIP FLOP WITH ACTIVE LOW
              ASYNCHRONOUS CLEAR AND PRESET. ILLEGAL OUTPUT OCCURS WHEN BOTH
              CLEAR AND PRESET ARE ACTIVE

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_N_RB_SB_X_NO (Q, QN, CP, RB, SB)

 INPUT      : CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED TOGGLE FLIP FLOP WITH ACTIVE LOW
              ASYNCHRONOUS CLEAR AND PRESET. ILLEGAL OUTPUT OCCURS WHEN BOTH
              CLEAR AND PRESET ARE ACTIVE
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_N_SB_RB (Q, QN, CP, RB, SB)

 INPUT      : CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED TOGGLE FLIP FLOP WITH ACTIVE LOW
              ASYNCHRONOUS CLEAR AND PRESET

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_N_SB_RB_NO (Q, QN, CP, RB, SB)

 INPUT      : CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED TOGGLE FLIP FLOP WITH ACTIVE LOW
              ASYNCHRONOUS CLEAR AND PRESET
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_N_TE_RB_SB (Q, QN, TE, CP, RB, SB)

 INPUT      : TE, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED TOGGLE FLIP FLOP WITH TOGGLE ENABLE
              AND ACTIVE LOW  ASYNCHRONOUS CLEAR AND PRESET

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_N_TE_RB_SB_NO (Q, QN, TE, CP, RB, SB)

 INPUT      : TE, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : NEGATIVE EDGE TRIGGERED TOGGLE FLIP FLOP WITH TOGGLE ENABLE
              AND ACTIVE LOW  ASYNCHRONOUS CLEAR AND PRESET
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_P_PLD (Q, QN, CP, PD, PLD)

 INPUT      : CP, PD, PLD

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED TOGGLE FLIP-FLOP WITH PARALLEL LOAD .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_P_PLD_NO (Q, QN, CP, PD, PLD)

 INPUT      : CP, PD, PLD

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED TOGGLE FLIP-FLOP WITH PARALLEL LOAD .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_P_RB (Q, QN, CP, RB)

 INPUT      : CP, RB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED TOGGLE FLIP FLOP WITH 
              ACTIVE LOW ASYNCHRONOUS CLEAR .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_P_RB_NO (Q, QN, CP, RB)

 INPUT      : CP, RB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED TOGGLE FLIP FLOP WITH 
              ACTIVE LOW ASYNCHRONOUS CLEAR .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_P_RB_PLD (Q, QN, CP, PD, PLD, RB)

 INPUT      : CP, PD, PLD, RB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED TOGGLE FLIP-FLOP
              WITH ACTIVE LOW ASYNCHRONOUS CLEAR AND PARALLEL LOAD .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_P_RB_PLD_NO (Q, QN, CP, PD, PLD, RB)

 INPUT      : CP, PD, PLD, RB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED TOGGLE FLIP-FLOP
              WITH ACTIVE LOW ASYNCHRONOUS CLEAR AND PARALLEL LOAD .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_P_RB_SB (Q, QN, CP, RB, SB)

 INPUT      : CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED TOGGLE FLIP FLOP WITH ACTIVE LOW
              ASYNCHRONOUS CLEAR AND PRESET

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_P_RB_SB_NO (Q, QN, CP, RB, SB)

 INPUT      : CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED TOGGLE FLIP FLOP WITH ACTIVE LOW
              ASYNCHRONOUS CLEAR AND PRESET
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_P_RB_SB_X (Q, QN, CP, RB, SB)

 INPUT      : CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED TOGGLE FLIP FLOP WITH ACTIVE LOW
              ASYNCHRONOUS CLEAR AND PRESET. ILLEGAL OUTPUT OCCURS WHEN BOTH
              CLEAR AND PRESET ARE ACTIVE

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_P_RB_SB_X_NO (Q, QN, CP, RB, SB)

 INPUT      : CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED TOGGLE FLIP FLOP WITH ACTIVE LOW
              ASYNCHRONOUS CLEAR AND PRESET. ILLEGAL OUTPUT OCCURS WHEN BOTH
              CLEAR AND PRESET ARE ACTIVE
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_P_SB (Q, QN, CP, SB)

 INPUT      : CP, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED TOGGLE FLIP FLOP WITH
              ASYNCHRONOUS SET ( ACTIVE LOW ) .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_P_SB_NO (Q, QN, CP, SB)

 INPUT      : CP, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED TOGGLE FLIP FLOP WITH
              ASYNCHRONOUS SET ( ACTIVE LOW ) .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_P_SB_RB (Q, QN, CP, RB, SB)

 INPUT      : CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED TOGGLE FLIP FLOP WITH ACTIVE LOW
              ASYNCHRONOUS CLEAR AND PRESET

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_P_SB_RB_NO (Q, QN, CP, RB, SB)

 INPUT      : CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED TOGGLE FLIP FLOP WITH ACTIVE LOW
              ASYNCHRONOUS CLEAR AND PRESET
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_P_TE_PLD (Q, QN, TE, CP, PD, PLD)

 INPUT      : TE, CP, PD, PLD

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED TOGGLE FLIP-FLOP WITH
              TOGGLE ENABLE AND  PARALLEL LOAD .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_P_TE_PLD_NO (Q, QN, TE, CP, PD, PLD)

 INPUT      : TE, CP, PD, PLD

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED TOGGLE FLIP-FLOP WITH
              TOGGLE ENABLE AND  PARALLEL LOAD .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_P_TE_RB (Q, QN, TE, CP, RB)

 INPUT      : TE, CP, RB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED TOGGLE FLIP FLOP WITH TOGGLE ENABLE
              AND ACTIVE LOW  ASYNCHRONOUS CLEAR 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_P_TE_RB_NO (Q, QN, TE, CP, RB)

 INPUT      : TE, CP, RB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED TOGGLE FLIP FLOP WITH TOGGLE ENABLE
              AND ACTIVE LOW  ASYNCHRONOUS CLEAR 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_P_TE_RB_PLDC (Q, QN, TE, CP, PD, PLD, RB)

 INPUT      : TE, CP, PD, PLD, RB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED TOGGLE FLIP-FLOP WITH
              TOGGLE ENABLE AND ACTIVE LOW ASYNCHRONOUS CLEAR
              AND SYNCHRONOUS PARALLEL LOAD .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_P_TE_RB_PLDC_NO (Q, QN, TE, CP, PD, PLD, RB)

 INPUT      : TE, CP, PD, PLD, RB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED TOGGLE FLIP-FLOP WITH
              TOGGLE ENABLE AND ACTIVE LOW ASYNCHRONOUS CLEAR
              AND SYNCHRONOUS PARALLEL LOAD .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_P_TE_RB_SB (Q, QN, TE, CP, RB, SB)

 INPUT      : TE, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED TOGGLE FLIP FLOP WITH TOGGLE ENABLE
              AND ACTIVE LOW  ASYNCHRONOUS CLEAR AND PRESET

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_FT_P_TE_RB_SB_NO (Q, QN, TE, CP, RB, SB)

 INPUT      : TE, CP, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE EDGE TRIGGERED TOGGLE FLIP FLOP WITH TOGGLE ENABLE
              AND ACTIVE LOW  ASYNCHRONOUS CLEAR AND PRESET
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_HALF_ADDR (S, CO, A, B)

 INPUT      : A, B

 OUTPUT     : S, CO

 FUNCTION   : HALF ADDER

 MODEL TYPE : GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_IAI_2_3 (Z, A, B, C)

 INPUT      : A, B, C

 OUTPUT     : Z

 FUNCTION   : TO IMPLEMENT THE LOGIC EQUATION  YN = ~( ~A & ~B & C )

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_IAOI_2_2 (Z, A, B, C, D)

 INPUT      : A, B, C, D

 OUTPUT     : Z

 FUNCTION   : TO IMPLEMENT THE LOGIC EQUATION  Z = ~( A & ~B || C & D ) 

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_IAO_2_2 (Z, A, B, C, D)

 INPUT      : A, B, C, D

 OUTPUT     : Z

 FUNCTION   : TO IMPLEMENT THE LOGIC EQUATION  Z = ( A & ~B || C & D ) 

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_IA_2_3 (Z, A, B, C)

 INPUT      : A, B, C

 OUTPUT     : Z

 FUNCTION   : TO IMPLEMENT THE LOGIC EQUATION  Z = ( ~A & ~B & C )

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_N (Q, QN, D, GN)

 INPUT      : D, GN

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH, GATED ACTIVE LOW  

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_N_CEB_NO (Q, QN, D, E, G)

 INPUT      : D, E, G

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH WITH ACTIVE LOW GATE & GATE ENABLE

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_N_CEB_RB_NO (Q, QN, D, E, G, RB)

 INPUT      : D, E, G, RB

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH WITH ACTIVE LOW GATE, ACTIVE LOW GATE ENABLE & ACTIVE LOW RESET

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_N_CEB_R_NO (Q, QN, D, E, G, R)

 INPUT      : D, E, G, R

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH WITH ACTIVE LOW GATE, ACTIVE LOW GATE ENABLE & ACTIVE HIGH RESET

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_N_CEB_SB_NO (Q, QN, D, E, G, SB)

 INPUT      : D, E, G, SB

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH WITH ACTIVE LOW GATE, ACTIVE HIGH GATE ENABLE & ACTIVE LOW SET

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_N_CEB_S_NO (Q, QN, D, E, G, S)

 INPUT      : D, E, G, S

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH WITH ACTIVE LOW GATE, ACTIVE HIGH GATE ENABLE & ACTIVE HIGH SET

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_N_CE_NO (Q, QN, D, E, G)

 INPUT      : D, E, G

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH WITH ACTIVE LOW GATE & ACTIVE HIGH GATE ENABLE

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_N_CE_R_NO (Q, QN, D, E, G, R)

 INPUT      : D, E, G, R

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH WITH ACTIVE LOW GATE, ACTIVE HIGH GATE ENABLE & ACTIVE HIGH RESET

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_N_CE_S_NO (Q, QN, D, E, G, S)

 INPUT      : D, E, G, S

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH WITH ACTIVE LOW GATE, ACTIVE HIGH GATE ENABLE & ACTIVE HIGH SET

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_N_NO (Q, QN, D, GN)

 INPUT      : D, GN

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH, GATED ACTIVE LOW 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_N_RB (Q, QN, D, GN, RB)

 INPUT      : D, GN, RB

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH, GATED ACTIVE LOW / CLEAR DIRECT 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_N_RB_NO (Q, QN, D, GN, RB)

 INPUT      : D, GN, RB

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH, GATED ACTIVE LOW / CLEAR DIRECT 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_N_RB_SB_X (Q, QN, D, GN, RB, SB)

 INPUT      : D, GN, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH, GATED ACTIVE LOW / CLEAR AND PRESET DIRECT 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_N_RB_SB_X_NO (Q, QN, D, GN, RB, SB)

 INPUT      : D, GN, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH, GATED ACTIVE LOW / CLEAR AND PRESET DIRECT 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_N_R_S_X (Q, QN, D, GN, R, S)

 INPUT      : D, GN, R, S

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH, GATED ACTIVE LOW / CLEAR AND PRESET DIRECT 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_N_R_S_X_NO (Q, QN, D, GN, R, S)

 INPUT      : D, GN, R, S

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH, GATED ACTIVE LOW / CLEAR AND PRESET DIRECT 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_N_SB (Q, QN, D, GN, SB)

 INPUT      : D, GN, SB

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH, GATED ACTIVE LOW / PRESET DIRECT  

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_N_SB_NO (Q, QN, D, GN, SB)

 INPUT      : D, GN, SB

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH, GATED ACTIVE LOW / PRESET DIRECT  
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_N_SB_RB (Q, QN, D, GN, RB, SB)

 INPUT      : D, GN, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH, GATED ACTIVE LOW / CLEAR AND PRESET DIRECT 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_N_SB_RB_NO (Q, QN, D, GN, RB, SB)

 INPUT      : D, GN, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH, GATED ACTIVE LOW / CLEAR AND PRESET DIRECT 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_N_S_R (Q, QN, D, GN, R, S)

 INPUT      : D, GN, R, S

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH, GATED ACTIVE LOW / CLEAR AND PRESET DIRECT 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_N_S_R_NO (Q, QN, D, GN, R, S)

 INPUT      : D, GN, R, S

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH, GATED ACTIVE LOW / CLEAR AND PRESET DIRECT 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_P (Q, QN, D, G)

 INPUT      : D, G

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH GATED ACTIVE HIGH 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_P_CEB_NO (Q, QN, D, E, G)

 INPUT      : D, E, G

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH WITH ACTIVE HIGH GATE & ACTIVE LOW GATE ENABLE

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_P_CE_NO (Q, QN, D, E, G)

 INPUT      : D, E, G

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH WITH ACTIVE HIGH GATE & GATE ENABLE

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_P_NO (Q, QN, D, G)

 INPUT      : D, G

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH GATED ACTIVE HIGH   
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_P_RB (Q, QN, D, G, RB)

 INPUT      : D, G, RB

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH, GATED ACTIVE HIGH / CLEAR DIRECT  

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_P_RB_NO (Q, QN, D, G, RB)

 INPUT      : D, G, RB

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH, GATED ACTIVE HIGH / CLEAR DIRECT . 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_P_RB_SB_X (Q, QN, D, G, RB, SB)

 INPUT      : D, G, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH, GATED ACTIVE HIGH / CLEAR AND PRESET DIRECT
              ILLEGAL OUTPUT OCCURS WHEN BOTH CLEAR AND PRESET ARE ACTIVE .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_P_RB_SB_X_NO (Q, QN, D, G, RB, SB)

 INPUT      : D, G, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH, GATED ACTIVE HIGH / CLEAR AND PRESET DIRECT .
              ILLEGAL OUTPUT OCCURS WHEN BOTH CLEAR AND PRESET ARE ACTIVE .              
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_P_R_S_X (Q, QN, D, G, R, S)

 INPUT      : D, G, R, S

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH, GATED ACTIVE HIGH / CLEAR AND PRESET DIRECT 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_P_R_S_X_NO (Q, QN, D, G, R, S)

 INPUT      : D, G, R, S

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH, GATED ACTIVE HIGH / CLEAR AND PRESET DIRECT 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_P_SB (Q, QN, D, G, SB)

 INPUT      : D, G, SB

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH, GATED ACTIVE HIGH / PRESET DIRECT  

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_P_SB_NO (Q, QN, D, G, SB)

 INPUT      : D, G, SB

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH, GATED ACTIVE HIGH / PRESET DIRECT .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_P_SB_RB (Q, QN, D, G, RB, SB)

 INPUT      : D, G, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH, GATED ACTIVE HIGH / CLEAR AND PRESET DIRECT .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_P_SB_RB_NO (Q, QN, D, G, RB, SB)

 INPUT      : D, G, RB, SB

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH, GATED ACTIVE HIGH / CLEAR AND PRESET DIRECT.
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_P_S_R (Q, QN, D, G, R, S)

 INPUT      : D, G, R, S

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH, GATED ACTIVE HIGH / CLEAR AND PRESET DIRECT 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_P_S_R_NO (Q, QN, D, G, R, S)

 INPUT      : D, G, R, S

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH, GATED ACTIVE HIGH / CLEAR AND PRESET DIRECT 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_SD (Q, QN, D1, C1, D2, C2)

 INPUT      : D1, C1, D2, C2

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH WITH SCAN TEST INPUTS 

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_SDA (Q, QN, D1, C1, D2, C2)

 INPUT      : D1, C1, D2, C2

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH WITH SCAN TEST INPUTS WITH DATA ANDed   

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_SDA_NO (Q, QN, D1, C1, D2, C2)

 INPUT      : D1, C1, D2, C2

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH WITH SCAN TEST INPUTS WITH DATA ANDed   
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_SDO (Q, QN, D1, C1, D2, C2)

 INPUT      : D1, C1, D2, C2

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH WITH SCAN TEST INPUTS WITH DATA ORed .  

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_SDO_NO (Q, QN, D1, C1, D2, C2)

 INPUT      : D1, C1, D2, C2

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH WITH SCAN TEST INPUTS WITH DATA ORed   
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_SD_NO (Q, QN, D1, C1, D2, C2)

 INPUT      : D1, C1, D2, C2

 OUTPUT     : Q, QN

 FUNCTION   : DLATCH WITH SCAN TEST INPUTS 
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_SD_O (Q, QN, D, C1, C2)

 INPUT      : D, C1, C2

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH WITH DUAL CLOCK INPUTS ( SCAN DESIGN )

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_LD_SD_O_NO (Q, QN, D, C1, C2)

 INPUT      : D, C1, C2

 OUTPUT     : Q, QN

 FUNCTION   : D-LATCH WITH DUAL CLOCK INPUTS ( SCAN DESIGN ) .
              This model is provided with Verilog NOTIFIER REGISTER feature .

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_L_N_SR_SB_RB (Q, QN, S, R, G, SB, RB)

 INPUT      : S, R, G, SB, RB

 OUTPUT     : Q, QN

 FUNCTION   : S-R LATCH WITH COMMON GATED INPUTS, AND ASYNCHRONOUS
              SET & RESET ( ACTIVE LOW ) .

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_L_P_S_R (Q, QN, S, R, G)

 INPUT      : S, R, G

 OUTPUT     : Q, QN

 FUNCTION   : POSITIVE LEVEL SENSITVE S-R TYPE LATCH 

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_L_RB_SB (Q, QN, S, R)

 INPUT      : S, R

 OUTPUT     : Q, QN

 FUNCTION   : S-R LATCH

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_L_R_S (Q, QN, S, R)

 INPUT      : S, R

 OUTPUT     : Q, QN

 FUNCTION   : S-R LATCH 

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_L_SB_RB (Q, QN, S, R)

 INPUT      : S, R

 OUTPUT     : Q, QN

 FUNCTION   : S-R LATCH

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_L_SR_SB_RB (Q, QN, S1, S2, SB, R1, R2, RB)

 INPUT      : S1, S2, SB, R1, R2, RB

 OUTPUT     : Q, QN

 FUNCTION   : S-R LATCH WITH SEPARATE GATE INPUTS AND ASYNCHRONOUS
              SET & RESET ( ACTIVE LOW ) / STANDARB DRIVE .

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_L_S_R (Q, QN, S, R)

 INPUT      : S, R

 OUTPUT     : Q, QN

 FUNCTION   : S-R LATCH 

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_MUX_1 (Q, A, SL)

 INPUT      : A, SL

 OUTPUT     : Q

 FUNCTION   : ONE TO ONE MULTIPLEXER WITH STORAGE .

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : module CDS_GEN_MUX_16X1 (Z, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, 

 INPUT      :     input   D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, 

 OUTPUT     : Z

 FUNCTION   : 16 TO ONE  NON-INVERTING MULTIPLEXER

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_MUX_1_INV (Q, A, SL)

 INPUT      : A, SL

 OUTPUT     : Q

 FUNCTION   : ONE TO ONE MULTIPLEXER WITH INVERTING OUTPUT
              AND STORAGE .

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_MUX_2_1 (Z, A, B, S)

 INPUT      : A, B, S

 OUTPUT     : Z

 FUNCTION   : NON-INVERTING TWO-TO-ONE MULTIPLEXER

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_MUX_2_1_INV (Z, A, B, S)

 INPUT      : A, B, S

 OUTPUT     : Z

 FUNCTION   : TWO-TO-ONE MULTIPLEXER WITH INVERTING OUTPUT 

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_MUX_2_2 (Z, A, B, S, SN)

 INPUT      : A, B, S, SN

 OUTPUT     : Z

 FUNCTION   : TWO TO ONE MULTIPLEXER, WITH TWO SELECT CONTROLS . 

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_MUX_2_2_INV (Z, SN, A, S, B)

 INPUT      : SN, A, S, B

 OUTPUT     : Z

 FUNCTION   : TWO TO ONE MULTIPLEXER, WITH TWO SELECT CONTROLS 
              AND INVERTING OUTPUT

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_MUX_3_2 (Z, D0, D1, D2, A, B)

 INPUT      : D0, D1, D2, A, B

 OUTPUT     : Z

 FUNCTION   : THREE TO ONE MULTIPLEXER WITH 2 SELECT CONTROLS
              AND INVERTING OUTPUT 

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_MUX_3_2_INV (Z, D0, D1, D2, A, B)

 INPUT      : D0, D1, D2, A, B

 OUTPUT     : Z

 FUNCTION   : THREE TO ONE MULTIPLEXER WITH 2 SELECT CONTROLS
              AND INVERTING OUTPUT 

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_MUX_4_2 (Z, D0, D1, D2, D3, A, B)

 INPUT      : D0, D1, D2, D3, A, B

 OUTPUT     : Z

 FUNCTION   : FOUR TO ONE MULTIPLEXER WITH 2 SELECT CONTROLS .

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_MUX_4_2_INV (Z, D0, D1, D2, D3, A, B)

 INPUT      : D0, D1, D2, D3, A, B

 OUTPUT     : Z

 FUNCTION   : FOUR TO ONE MULTIPLEXER WITH 2 SELECT CONTROLS AND INVERTING OUTPUT .

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_MUX_5X1 (Z, D0, D1, D2, D3, D4, A, B, C)

 INPUT      : D0, D1, D2, D3, D4, A, B, C

 OUTPUT     : Z

 FUNCTION   : 5 TO ONE NON-INVERTING MULTIPLEXER

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_MUX_8X1 (Z, D0, D1, D2, D3, D4, D5, D6, D7, A, B, C)

 INPUT      : D0, D1, D2, D3, D4, D5, D6, D7, A, B, C

 OUTPUT     : Z

 FUNCTION   : 8 TO ONE NON-INVERTING MULTIPLEXER

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_O2_AI2_AI (Z, A, B, C, D)

 INPUT      : A, B, C, D

 OUTPUT     : Z

 FUNCTION   : 2-INPUT OR and 2-INPUT NAND  into 2-INPUT NAND 

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_OAI_2_2 (Z, A, B, C, D)

 INPUT      : A, B, C, D

 OUTPUT     : Z

 FUNCTION   : 2-WIDE 2-INPUT OR into 2-INPUT NAND 

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_OAI_2_2_2_2 (Z, A, B, C, D, E, F, G, H)

 INPUT      : A, B, C, D, E, F, G, H

 OUTPUT     : Z

 FUNCTION   : 4-WIDE 2-INPUT OR into 4-INPUT NAND

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_OAI_2_3 (Z, A, B, C, D, E)

 INPUT      : A, B, C, D, E

 OUTPUT     : Z

 FUNCTION   : 2-INPUT OR and 3-INPUT OR into 2-INPUT NAND 

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_OAI_3_3 (Z, A, B, C, D, E, F)

 INPUT      : A, B, C, D, E, F

 OUTPUT     : Z

 FUNCTION   : 2-WIDE 3-INPUT OR into 2-INPUT NAND 

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_OA_2_2 (Z, A, B, C, D)

 INPUT      : A, B, C, D

 OUTPUT     : Z

 FUNCTION   : 2-WIDE 2-INPUT OR into 2-INPUT AND 

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_OA_2_3 (Z, A, B, C, D, E)

 INPUT      : A, B, C, D, E

 OUTPUT     : Z

 FUNCTION   : 2-INPUT OR and 3-INPUT OR into 2-INPUT AND 

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_OA_3_3 (Z, A, B, C, D, E, F)

 INPUT      : A, B, C, D, E, F

 OUTPUT     : Z

 FUNCTION   : 2-WIDE 3-INPUT OR into 2-INPUT AND 

 MODEL TYPE : UDP
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_RAM1 (ZN, Q, D, WR, WRN, RD)

 INPUT      : D, WR, WRN, RD

 OUTPUT     : ZN, Q

 FUNCTION   : 1-BIT RAM , WITH ADDED THREE-STATE OUTPUT

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_RAM1_QN (ZN, QN, D, WR, WRN, RD)

 INPUT      : D, WR, WRN, RD

 OUTPUT     : ZN, QN

 FUNCTION   : 1-BIT RAM , WITH ADDED THREE-STATE OUTPUT

 MODEL TYPE : UDP and GATE
                       
===============================================================================
===============================================================================

 CELL NAME  : CDS_GEN_SUB1 (D, CO, A, B, CI)

 INPUT      : A, B, CI

 OUTPUT     : D, CO

 FUNCTION   : 1 - BIT SUBTRACTOR  

 MODEL TYPE : UDP
                       
===============================================================================
