GENERIC LIBRARY: VERSION RELEASE_2.0
Release Date   : 17th February 1992

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This version of the generic library i.e. release2.0, has 
certain enhancements and bug fixes over the previous version 
i.e. release_1.0b. Also, the UDPs used by certain cells have
been upgraded to take care of pessimism cases critical to the 
functionality of these cells.The following are the enahancements
made in this Version :           
    
  1.Support of State dependent Path-Delays.

    Conformance of the model to the Ground Rules for SDPDs. 
    The model is certified for correct delay selection under 
    various input conditions.

  2. Addition of New models to the existing library. The list
     of such models are provided in the NewModels.list.

  3. Changing the two UDP definition for some sequential models so as
     to optimize  in terms of memory and speed.  By doing so we are 
     achieving synthesis compatibility also, by providing a single UDP
     definition with a buf/not configuration
    
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GENERIC LIBRARY contains a set of technology independent generic 
models in Verilog which can be shared across a variety of libraries. 

Product compatibility:

           Verilog  1.6a .
           Veritime 1.2b.4
 

Model structure information :
 
         Each generic model is defined as a module. The module name 
         tells the functionality of the model.
    
         Port name order in the module header is outputs, inputs, inouts., 
         All ports are scalars.

         The models are built using a combination of Verilog Gate and
         User Defined Primitives. They have been modeled to obtain an
         optimum combination of accuracy and efficiency. The UDPs
         are put in the directory 'udps'.
         
         There is a parameter " vlib_flat_module " in the modules to tell
         the VeriLib delay distributor whether the generic model should be
         flattened and the UDP be instantiated directly in the parent 
         module or not. 


Delay information : 

         All the models have been provided with  
         Delay  path and timing path templates inside 
         the specify block for Verilog/VeriTime, which can be 
         cross-referenced using Verilib to produce
         technology dependent models from these models.
         The Delay values in the Delay paths are given to be
         unity as dummy values.

         Timing Checks in the case of LATCHES have been done on
         the inactive edge of the clock.

NOTIFIER REGISTER MODELS :

     Functionality of Sequential Cells has also been made
     dependent on timing in the case of the following models
            ?*_NO.v 
     A timing violation causes the outputs to go to VERILOG 
     'x'-state. A subsequent valid set of inputs affecting
     the outputs makes the outputs come out of 'x'-state. 
     This is done using the NOTIFY_REGISTER feature of VERILOG 
     Timing tasks.




