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| XILINX APPLICATIONS NOTE XAPP044O-V0.01                  LDC-12-09-94 |
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README file for the XC4000A Example Design FIFOTOP:
===================================================

Note:  A more detailed description of this application can be found in
Section 8 of the Xilinx Data Book.  This design is an implementation of 
the high-performance FIFO, not the expandable FIFO.

 This FIFO design achieves high performance by using a read-modify-write
operation.  Write Enable is asserted every cycle.  "Non-write" cycles are
permitted by rewriting existing data into the RAM.
 
***
  The rest of this readme file has yet to be written. 
  The design was implemented and simulated by Ruth Mayeda based on the app 
note by Bernie New. It was afterward slightly modified for cosmetic reasons. 
The Viewlogic version of these schematics have been given to several customers. 
One of these customers reported that the push/pop arbitrator was generating 
full or empty signals at the wrong time, but since he did not need the func-
tionaliy he simply deleted part of the logic.  No other customers have reported 
problems, and Ruth and I could not find anything wrong with the schematics.  
Just thought you should know.
 
  If you ever do enough work with this design that you think it should be
released, please let us know.  You might take a shot at completing this 
readme file (using the standard format).   
 
  Thanks!  Enjoy.
  loisc (lois cartier)

***


Files included in the XAPP044O directory:
-----------------------------------------

README            This README file
FIFOTOP.SCH       Example of a top-level schematic showing IO pads, BUFGS,
		  and assignment of PRIORITY signal.
PUSHPOPA.SCH      Push/Pop arbitration logic.
ADDRGEN.SCH       Address and flag generation block.
WADDR.SCH         Write-address generation.
WRITE_SR.SCH      Write-address shift register, set to initialize to 1000.
RADDR.SCH         Read-address generation.                       
READ_SR.SCH       Read-address shift register.  This component can be replaced
		  with a standard library component (SR4CE).
RAMBLOCK.SCH      RAM operational block.  This block contains the address
		  MUX, and input and output data registers.
M8-4.SCH          Address select block.
MYRD4.SCH         RAM address register.  This component can be replaced with
		  a standard library component (FD4CE).
MYRAM.SCH         16-word, 8-bit RAM.  This component can be replaced with a
		  standard library component (RAM16X8).
MYRD8.SCH         Input/Output data registers.  This component can be replaced
		  with a standard library component (FD8CE).

FIFOTOP.LCA       Placed and rounted LCA file for design.
*.INF		  INF files for each schematic.
XNF\*.XNF         Xilinx Netlists for schematics.



