This XC9000 Mentor Interface is used to implement Mentor schematic designs
for XC9000 CPLD devices on Sun4 or HPPA workstation. It also prepares 
timing simulation schematics of the implemented design.

REQUIREMENTS

To process XC9000 designs using this interface, you also need the following
software installed on your system:

  1. XC9000 Implementation software (DS560)
  2. Xilinx Mentor v8 Interface and Libraries (DS344)

INSTALLATION INSTRUCTIONS

The XC9000 Mentor Interface may be installed into either your existing
XC9000 Implementation software (DS560) area or a separate directory.

If you install to a separate directory, update the following environment
variables.

For Sun4:

        set path = (<mentor_path>/bin/sparc $path)
        setenv XACT <mentor_path>:$XACT

    Where <mentor_path> is the directory where this Mentor Interface
    is installed.


For HPPA:

        set path = (<mentor_path>/bin/hppa $path)
        setenv XACT <mentor_path>:$XACT

    Where <mentor_path> is the directory where this Mentor Interface
    is installed.

DESIGN IMPLEMENTATION

To implement a design for an XC9000 device:

  1. Prepare a Mentor schematic using the XC7000 library symbols provided
     in the Xilinx Mentor v8 Interface and Libraries (DS344).

  2. Save your schematic, but do NOT use the "pld_men2xnf8" or "pld_xemake"
     commands in the Mentor environment to process your design.

  3. In a UNIX command window, execute the following command while in the
     project directory:

        xepld <design>

     where <design> is the name of your top-level design schematic.

The xepld command reads the Mentor schematic file, translates it to an
XNF-formatted netlist and implements the design.

By default, the xepld command automatically selects an XC9000 device to
fit your design, if possible. If you wish to select a specific target
device, you can use the "-p <part_type>" option on the xepld command line.

To get a list of all the available xepld command options, type:

        xepld -help

The XC9000 Implementation software produces the following output files:

  1. Fitter report (including pinout): <design>.rpt
  2. Static timing report: <design>.tim
  3. Programming bit-map: <design>.jed
  4. Timing simulation netlist: <design>_tim.xnf

TIMING SIMULATION

To perform timing simulation using QuickSim on a completed design, execute
the following command while in the project directory (do NOT use the
"pld_timsim8" command in the Mentor environment):

        xepldsim -mentor <design>

The xepldsim command reads the <design>_tim.xnf file generated by the xepld
command and translates it into a new Mentor schematic named <design>_tim.
To simulate, invoke QuickSim on the <design>_tim schematic.

For more details on XC9000 schematic design techniques and the xepld and 
xepldsim commands, refer to the XEPLD Schematic Design Guide provided with
the XC9000 Implementation software (DS560).
