INSTALLATION:
Install TIM.EXE and TIMERPT.EXE in your \XACT directory.

DESCRIPTION:
This utility generates a static timing report from an XC7000 design database
file (.VMH or .VMD). TIMERPT.EXE generates an XC7000 timing simulation .XNF
file, then calls the report generator TIM.EXE.

OPERATION:
To create the timing report, type the following at the system prompt:
                     
                     timerpt [options] design_name

The timing report has three options:

The -f option is used to show the data path and clock path delays used to
calculate the SETUP-TO-CLOCK time. Usually, this info is not needed.

The -w option creates 132 column reports. The default width is 80 columns.

The -o file_name option creates a file_name.XNF file instead of a 
design_name.XNF file. If you don't use this option, the timing analyser 
overwrites any existing design_name.XNF file.

EXAMPLE:

To create a 132 column report which includes clock and data input timing
(overwriting the design_name.XNF file) enter the following:

                     timerpt -w -f design_name

REPORT FORMAT:

The report contains a summary title page and subsequent detailed
pages.  The summary title page has a summary at the top and then lists
delay summaries of various types.

The summary section, the delay-summary section and the detailed section
describe 4 different types of delays:

1. Combinational pad-to-pad delays.  This represents the delay between
pads using purely combinational paths.  This includes any paths through
the asynchronous set or reset of a register.  The program computes the 
worst-case delay between each pair of pads.

2. Setup delays.  This represents the setup delay between clocks 
and data inputs of registers.  The program looks at each register 
in the design and traces back the d-input and clock inputs until 
it reaches an input pad.  It displays setup times between all pads 
with a d-input path and all pads with a clock path.

During path tracing, the program follows clock paths.  If it
traces the data-input back to the Q-output of an earlier register, it
proceeds to trace back the clock inputs of that earlier register.

The setup delay represents the worst case setup condition between two
input pads.  Each setup condition represents the longest d-input delay
less the shortest clk-input delay.

3. Clock-Pad-to-Output_Pad delays.  This represents the worst case
path from an input pad, to a register clock input, and to an output pad.

4. Cycle Times.  The report only print cycle times for two communicating
registers that share the same clock.  Note that you should take into
account the setup-time and clock-to-output time yourself when
considering the setup time.

The report does NOT show a cycle time for non-communicating registers.

Note that we cannot show the "real" register names in the cycle time
table.  You will have to look in the .map file to see the actual
register name. 
