GENERAL INFORMATION:

Design:         Pentium/Synchronous DRAM Controller
Req'd software: XEPLD v5.0
                XABEL v5.0 
Platforms:      PC-DOS, Sun, HP700
Target device:  XC7354-44 for PENTIUM
                XC7318-44 for SELECTOR

This example demonstrates a typical XEPLD behavioral design flow. The 
logic of a DRAM controller is expressed using 2 generic ABEL-language 
equation files, pentium.abl and selector.abl. PENTIUM contains the control
logic, while SELECTOR contains the address multiplexor.

The 2 ABEL files are first compiled and translated to PLUSASM using the 
XABEL compiler. You can compile the files under the XABEL interface, which 
can be invoked by selecting DesignEntry -> XABEL in the XDM menu. Then run 
the PLUSASM (.pld) files through the EPLD fitter. To run the fitter, select 
Fitter -> FITEQN in the XDM menu.

The fitter produces several report files, including Resources (.res), 
Mapping (.map), Pinlist (.pin) and Partitioning (.par).

If you only have ABEL, without the Xilinx XC7000 fitter from Data I/O, you can 
generate a PLUSASM compatible equation file from within ABEL by using the XFER 
utility to translate to .PDS format. DO NOT USE THE PLUSASM OR XILINX PDS 
FORMAT IN THE ABEL XFER WINDOW. 

Then create a PLUSASM compatible top level file using the PALCONVT utility in 
XDM. Add the declarations contained in the PLUSASAM PROPERTY statements of 
the ABEL code to the top level file. Edit the OUTPUTPIN and NODE signal lists 
as instructed in the XACT XEPLD BEHAVIORAL DESIGN GUIDE, then process the
design with FITEQN.

