This file contains instructions for use and limitations of
"I2X.EXE". This file converts INTEL iFX design files into
Xilinx EPLD design files.

Procedure:

1. First, compile the iFX design using PLDshell. This will generate
a design_name.rpt file.
2. Run I2X by typing "i2x design_name" <return>. Make sure that I2X.EXE
and the design_name.rpt file are in the same directory.
3. If the design uses RAM or ROM a message is printed to the screen.
On-chip RAM or ROM requires a Xilinx XC4000 FPGA. You should call your 
local Xilinx representative for more information.
4. Open the PLD file in your favorite ASCII editor and check for range
delimiters. If there are any in the file follow the instructions in the
LIMITATIONS section below.
5. Open XDM (the Xilinx Design Manager) and select a Xilinx EPLD.
(For Intel iFX780 devices this will usually be an XC73108 in an 84 or 
160 pin package)
6. Select FITEQN and then PALCONVT from the pull-down menus. 
7. From this point on follow the Xilinx XEPLD reference guide for
design flow information.

LIMITATIONS

If the design file contains range delimiters such as "ADDR[3:0]", you
must edit the resulting design_name.pld file to expand the delimiters.
To do this delete the delimiter statement and type a signal name for
the range. i. e. ADDR3 ADDR2 ADDR1 ADDR0

This utility deletes the first 17 characters on a line in the PIN 
declarations section. If the actual signal name begins at column 17
or less, add some blank space in front ogf the PIN  keyword. If you 
don't do this some or all of the signal names are liable to be erased.
If this does happne don't fear. Cut and paste the signal names out of 
the design_name.i2x file which is created as an intermediate step.

This conversion utility is not set up to handle bi-directional pins.
Xilinx EPLDs DO support this feature. In general, the pin must be 
declared as an IOPIN and when the input signal is used on the right 
side of an equation it must havea .PIN extension. Please see the 
XILINX XEPLD REFERENCE GUIDE for more information on this topic.  

There are also several register types which are not directly supported
such as J-K and S-R. Xilinx has placed example PLD files in the 
XACT\EXAMPLES\BEHAVIORAL\LIBRARY sub-directory. These will show you 
the correct method implement these register types in a Xilinx EPLD.

If you have any comments or questions on this utility please send E-mail to:

patk@xilinx.com

DISCLAIMER

XILINX IS PROVIDING THIS SOFTWARE (I2X.EXE) TO USERS OF XILINX PRODUCTS
SOLEY IN SUPPORT OF THOSE PRODUCTS. XILINX DOES NOT ASSUME ANY LIABILITY
ARISING OUT OF THIS UTILITY OR ITS USAGE. XILINX IS NOT RESPONSIBLE FOR
ANY ERRORS OR DEFECTS IN THIS SOFTWARE PROGRAM. XILINX EXPRESSLY DISCLAIMS
ANY WARRANTIES, EXPRESSED OR IMPLIED, INCLUDING WARRANTY OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE. 
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