Contents of /pub/applications/3rdparty

Applications Relating to Third Party interfaces

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  Filename                Size             File Description
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xsi_verilog.tar.Z       2974KB  Verilog design examples for "HDL Synthesis
                                Design Guide for FPGAs". Uncompress and
                                tar -xf to extract.
vstbsim.zip              195KB  Board-level simulation with OrCAD VST v1.20
