Contents of /pub/applications/3rdparty
Applications Relating to Third Party interfaces ============================================================================= Filename Size File Description ============================================================================= xsi_verilog.tar.Z 2974KB Verilog design examples for "HDL Synthesis Design Guide for FPGAs". Uncompress and tar -xf to extract. vstbsim.zip 195KB Board-level simulation with OrCAD VST v1.20