 _______________________________________________________________________
|                                                                       |
| XILINX APPLICATION NOTE:  Implementing FIFOs in XC4000E RAM-V1.01     |
| Version 1.00                                             LDC-06-21-95 |
| Version 1.01 Adjusted Timespecs and timing results                    |
|              based on Preliminary speedsfile             LDC-10-12-95 |
|_______________________________________________________________________|

README file for the XC4000A FIFO Designs FTOP* and FIFO RPMs FIFO*:
===================================================================

Note: A more detailed description of this application can be found in the
Xilinx Application Note "Implementing FIFOs in XC4000E RAM," available
by calling the Xilinx Hotline at 1-800-255-7778.

Five VIEWlogic RPMs are included, different versions of a 16x32 FIFO.  
They can be used as is; however, for most applications you will need to 
edit the control logic to achieve the desired functionality.  FIFOs are 
very application-specific.  The FIFOs as supplied are Write FIFOs for a 
PCI interface.

Just place the RPM in your schematic, with appropriate Timespec attributes 
as demonstrated in the top-level schematic supplied with each RPM.  All 
RPMs are 6 CLBs wide and 8 high, with the exception of FIFOS, which is 4 
CLBs wide and 8 high.

FIFOA, FTOPA
------------

This asynchronous FIFO can be used in an XC4000 or XC4000H device 
as well as the XC4000E.  It uses the level-sensitive RAM mode, and gives 
an operating frequency of about 31 MHz in the XC4005E-3.  

This FIFO runs at half the frequency of the input clock; therefore
a 62 MHz clock must be available as the input clock.

FIFOR, FTOPR
------------

This asynchronous FIFO is a "risky" version of FIFOA.  The timing is 
similar, except that it runs at the same frequency as the input clock,
rather than at half speed.  The tradeoff is that the Write Enable pulse
is a glitch internally generated by the falling edge of the input clock.

Due to the inherently risky nature of using "glitches" in FPGA designs,
this version of the design is NOT recommended for production designs.

Operating frequency should be about 30 MHz in an XC4005E-3.  XC4000 and 
XC4000H are supported as well as the XC4000E, since level-sensitive RAM 
mode is used.

FIFOE, FTOPE
------------

This asynchronous FIFO is a plug-in replacement for FIFOA or FIFOR.  However, 
it runs at about twice the speed.  Edge triggered ("synchronous") RAM is
used.  Only the XC4000E can be used for this design.

FIFOS, FTOPS
------------

This version of the FIFO is synchronous: it does not register the address
and data input lines.  Otherwise, it is very similar to FIFOE.  Removing
the registers makes this RPM smaller than the other versions.  Only the
XC4000E is supported.

FIFOD, FTOPD
------------

This synchronous FIFO is the only one that uses dual-port RAM.  Because
of the dual-port mode, the size of the RPM increases again to 6 columns
by 8 rows.  The operating frequency should exceed 66 MHz.  In addition,
simultaneous Read and Write operations are supported.

Design files included in file FIFLES.ZIP:

  SCH\FIFOA.1,2     RPM for Asynchronous FIFO
  SCH\FIFOA.1,2     RPM for Risky Asynchronous FIFO
  SCH\FIFOA.1,2     RPM for Edge-Triggered Asynchronous FIFO
  SCH\FIFOA.1,2     RPM for Synchronous FIFO
  SCH\FIFOA.1,2     RPM for Dual-Port Synchronous FIFO
  SCH\FTOPA.1       Top-level Viewlogic schematic for FIFOA
  SCH\FTOPR.1       Top-level Viewlogic schematic for FIFOR
  SCH\FTOPE.1       Top-level Viewlogic schematic for FIFOE
  SCH\FTOPS.1       Top-level Viewlogic schematic for FIFOS
  SCH\FTOPD.1       Top-level Viewlogic schematic for FIFOD
  SCH\C4U.1,2       4-bit Up Counter used for address pointers
  SCH\C4UD.1,2      4-bit Up-Down Counter used in status block
  SCH\FD16A.1       16-bit data register, 2 FFs per CLB
  SCH\FD16D.1       16-bit data register, 1 FF per CLB
  SCH\FD32A.1       Two 16-bit data registers
  SCH\M2_1x4.1,2    Four 2-1 MUXes
  SCH\RM16X16A.1    16x16 Level-Sensitive RAM array
  SCH\RM16X16D.1    16x16 Dual-Port, Edge-Triggered RAM array
  SCH\RM16X16S.1    16x16 Edge-Triggered RAM array
  SCH\RM16X32A.1    Two 16x16 Level-Sensitive RAM arrays
  SCH\RM16X32D.1    Two 16x16 Dual-Port, Edge-Triggered RAM arrays
  SCH\RM16X32S.1    Two 16x16 Edge-Triggered RAM arrays
  
  FTOP*.LCA         Placed and routed LCA file for each top-level design
  FTOP*.XRP         XDelay report file for each routed design
  SYM\*.1           VIEWlogic symbols for each schematic

  USEFUL\FTOP*.CMD  VIEWsim command files for each top-level design
  USEFUL\FTOP.XTM   XDelay template file for analyzing timing
  USEFUL\RUNFILE    Unix Shell script to implement all 5 top-level designs
                    and create XDelay reports
  USEFUL\RUNVFILE   Unix Shell script to create simulation netlists for 
                    all 5 top-level designs

Software Versions used:
  DS390 Version 4.1.3a Viewlogic and Interface
