Contents of /pub/swhelp/cadence

Files/Patches/Information on the Xilinx-Cadence Interface

=============================================================================
  Filename                Size             File Description
=============================================================================

vconfig03.23-p007su...    20KB	Two-part patch for Verilog-XL v2.1.2 to
verilogxl02.20-s018...  4044KB	fix core dump problem when +neg_tchk
                                option is specified. The two archives
                                are needed to compile a configurable
                                version of Verilog-XL (one that can be
                                linked to PLI routines).
vlogintdoc.ps.Z	         172KB  Full documentation for ES-VERILOG v5.2.0
                                Interface to Verilog-XL (PostScript format) 
                                For SunOS 4.x
xil_vlog_intfc.hp7...    883KB  ES-Verilog interface for 2K, 3K, 4K,
                                4KE, 5K and 7K architecturess from 
                                XACTstep Core Tools v5.2.1 for work-
                                stations--(HP7)
xil_vlog_intfc.sun4...  1043KB  ES-Verilog interface for 2K, 3K, 4K,
                                4KE, 5K and 7K architectures from
                                XACTstep Core Tools v5.2.1 for work-
                                stations--(Sun4)
pre5cds3.pdf             37 kB  Application note describing
			        workarounds for using the pre-
			        Unified / pre-9404 Cadence
			        Concept and Composer libraries
			        and interface with XACT 5.x.
				Solution #:  1716
                   	        For All Platforms
				Uploaded: 03-13-97
