Although power is the item of discussion here, another important factor is performance.

The major contribution to power dissipation is clock frequency. The higher the clock frequency, the more power is dissipated due to capacitive charging and discharging of internal routing lines and transistor gates.

Every package has a certain power limit that it can dissipate while maintaining the die at a safe temperature (typically below 125C). Since non-segmented routing dissipates about 3x the power that segmented routing does (based on measurements taken at Xilinx), it follows that given the same cooling conditions, the segmented architecture can run at 3x higher in frequency than the non-segmented architecture.

Hammer this point hard. It is one of the strongest points against the Altera architecture.