Using the advanced process technology discussed earlier, Xilinx will continue to displace gate arrays and provide programmable logic at extremely high densities.

Enhancements in both FPGA architecture and software are planned in order to achieve the high densities depicted.

It is worth noting that this is what the process technology will support. We will only build these very large gate count devices if the market supports them.

Some customers may multiply out the 150k logic cells at 12 gates per logic cell and find it to be a bit short of 2M gates. Adding the gates required to perform JTAG (700 gates per I/O) easily brings the total to 2M gates.