The process migration described earlier will shrink die sizes to the point where many FPGAs will be pad limited. This means the die size will be constrained not by how many gates of logic are required but rather by the number of I/O pins required. This means that a gate array would have the same size as the equivalent gate density FPGA.

This means there will be little need for the smaller gate density gate arrays even in multi-million quantities since the price of the gate array and FPGA would be equivalent. We are starting to see evidence of this with the XC5202 today. The density of this die size equivalence is increasing year by year.

This will gradually cause FPGAs to become the mainstream technology of choice for logic. Gate arrays will be forced to the extremely high gate densities and CPLD power dissipation will always be too high to support any densities higher than about 10k gates.