Xilinx software solutions combine state-of-the-art timing driven design implementation software technology and easy-to-use graphical tools to enable push-button design flows.

Design Creation -

- Automatically accepts EDIF and XNF netlists

- Only retranslates netlist if it has changed since last translation

MAP - The mapper takes a logic design, made up of gates and FFs,

and efficiently maps those elements into the physical CLBs and

IOBs of the device.

PAR - Place And Route

- Recognition and Placement of Design Structure

- Adders, Counter, etc.

- Datapath