Check Point Verification is designed to allow the user the flexibility to check the design based on the users needs. For some designers, capturing the design, implementing the design, then verifying the design in-circuit is all that is necessary. For others, simulation and timing verification after every design step is a requirement. The check point verification system gives each of these users the ability to customize the verification steps which will be used during the design cycle.

Gate-Level Simulation / RTL Simulation

• The VHDL/Verilog RTL models give the user the ability to simulate the entire design before synthesizing.
• Gate Level simulation gives the user the confidence that the design is working before submitting the design to implementation (ngdbuild / mapping / PAR) resources.

Integrated Design Rule Check

Throughout the design process, Check Point Verification provides the user with statistics and hints about the design. Identification of design attributes or problems gives the designer the opportunity to change the design early in the implementation phase, when changes are much easier to accommodate.

Preliminary Timing

Preliminary Timing is sometimes referred to as either “Block delays” or “pre-layout” timing. Preliminary timing provides the data necessary to perform timing simulations when all timing information is not yet known. Preliminary timing includes only the delays associated with FPGA’s logic resources (CLB,TBUF,IOB,etc) and not the associated routing delays.

Post-Layout

Post layout timing simulation and static timing analysis gives the designer a look at the final timing information. A complete device level simulation and verification can take place using the full timing models available at this check point.