Xilinx will have 10 devices (4005, 4010, 4013, 4020, 4028, 4036, 4044, 4052, 4062, 4085) available on 0.35u by the end of 1H97. This comprises the entire 3.3 volt XC4000XL family.

This 3.3 volt family will be higher performance than any 5 volt FPGA available. It will also dramatically reduce the already low power dissipation of Xilinx’ non-segmented architecture. As shown in the graph, prices will be as low or lower than the equivalent 5 volt devices.

The horizontal axis is marked with both logic cells and gates. Because the counting of gates is so subjective and some of our competitors have taken much liberty in how they count gates, we have included logic cell counts.

One logic cell = One 4-input LUT + One FF

If customers are ever confused about gate counting, lead first with the Altera divide by 2 strategy. If that is not successful, then fall back to comparing the number of logic cells between devices. This is a very defensible position.

ORCA gates match reasonably well to Xilinx gates.

You can then talk about the HardWire savings today and the fact that HardWire provides the largest cost savings for the largest devices today and the largest devices of the future.