Notes:

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• For USB we started our system analysis by looking at the design from the point of view of speed. While the Full-Speed USB is “only” 12 MHz, the design involves several blocks that run at 4X the basic rate, or 48 MHz. This is a 4X oversampling of the serial NRZI USB data/clock signal.
• What we want to do is understand the design both within blocks of logic, and between blocks of logic. We will then apply TIMESPEC constraints to these relationships.
• Pipeline registers - registers that exist or may have to be added to the outputs of blocks of logic - are used to apply TIMESPEC constraints between blocks of logic.