Notes:

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• We’ve just looked at some of the general principles of Xilinx design flow - now back to the specific USB design example.
• These are some techniques that were used to get the timing.
• In this design we mostly used the TIMESPEC/timing constraint method. This “pulled” the correct logic together for placement. However, in the actual design (we will mention at the end - the Inventra core) a simple, broad physical layout constraint was used to floorplan the back-end, system interface logic (which we are not really talking about in this section).
• Lock Pins
• Pipeline registers: as noted earlier, these registers were added in the HDL code so that TIMESPEC constraints could be added between system blocks.
• We let Synopsys make the choice, given the timing constraints, to choose the state machine encoding.