XC9500 Software Flows
XABEL
Mentor
Foundation
|
Cadence
Exemplar
|
v1.0
Introduction
This application brief shows how to
use XABEL to design with XC9500 CPLDs. System configuration issues and
software flows are discussed for the PC, Sun and HP platforms.
Software Required
XACT-CPLD (DS-560) XC9500 Core Software
XABEL (DS-371) Xilinx Abel
System Configuration
PC
The XC9500 software should be installed
in a separate directory from any other Xilinx production software. When
designing with XC9500 devices, this directory should appear in the path
statement and xact variable before any other Xilinx software. Assuming
each software package is installed it's default directory (c:\xact9000
for XACT-CPLD and c:\xact for XABEL), the path should include: c:\xact9000;c:\xact
The XACT variable should be set as
follows: set xact=c:\xact9000;c:\xact
Remember to remove \XACT9000 from the
path and xact variable when designing with XC7000 CPLDs or Xilinx FPGAs.
Sun and HP
The XC9500 software should be installed
in a separate directory from any other Xilinx production software. When
designing with XC9500 devices, this directory should appear in the path
statement and XACT environment variable before any other Xilinx software.
Assuming each software package is installed it's default directory (/xact9000
for XACT-CPLD and /xact for XABEL), the UNIX environment variables for
the Sun should be:
set path = (/xact9000/bin/sparc $path)
setenv XACT /xact9000:$XACT
The UNIX environment variables for
the HP700 should be:
set path = (/xact9000/bin/hppa $path)
setenv XACT /xact9000:$XACT
Design Flow
XABEL does not yet have the XC9500
family in it's device selector menu. However, XC7000 design.PLD
files generated by XABEL can be used for XC9500 devices without modification
and without any loss in design efficiency.
Step 1: Enter the design and process
it using XABEL as you would for an XC7000 design.
Step 2: Invoke XACT-CPLD and process the design using design.PLD as the source file. The device type in the design.PLD file chip statement will be overridden by the XC9500 device type selected when the design is compiled.
v1.1
Introduction
This application brief shows how to
use Mentor and Autologic to design with XC9500 CPLDs. System configuration
issues and software flows are discussed for the Sun and HP platforms.
Software Required
XACT-CPLD (DS-560) XC9500 Core Software
MEN9K.TAR Mentor XC9500 Interface Patch
Mentor Interface (DS-344) Mentor v8
(XC7000) Interface and Libraries
MEN9K.TAR is available on the Xilinx FTP site.
System Configuration
The XC9500 software and interface patch
should be installed in a separate directory from any other Xilinx production
software. When designing with XC9500 devices, this directory should appear
in the path statement and XACT environment variable before any other Xilinx
software. Assuming each software package is installed it's default directory
(/xact9000 for XACT-CPLD and /xact for the Mentor interface), the UNIX
environment variables for the Sun should be:
set path = (/xact9000/bin/sparc $path)
setenv XACT /xact9000:$XACT
The UNIX environment variables for
the HP700 should be:
set path = (/xact9000/bin/hppa $path)
setenv XACT /xact9000:$XACT
Remember to remove /xact9000 from the
path and XACT environment variable when designing with XC7000 CPLDs or
Xilinx FPGAs.
Schematic Design Flow
This design flow relies on the Xilinx
XC7000 libraries for schematic capture and simulation. To implement a design
for an XC9500 device:
Step 1: Prepare a Mentor schematic
using the XC7000 library symbols provided in the Xilinx Mentor v8 Interface
and Libraries (DS-344). Avoid using arithmetic symbols (adders and accumulators)
COMPM4 and COMPM8 magnitude comparators, input latches and the BUFCE input
register clock enable buffer since these symbols use XC7000 specific resources.
Step 2: Save the schematic, but DO
NOT use the "pld_men2xnf8" or "pld_xemake" commands
in the Mentor environment to process the design.
Step 3: In a UNIX command window, execute the following command while in the project directory:
xepld <design>
where <design> is the name of
the top level schematic. The xepld command reads the Mentor schematic file,
translates it to an XNF formatted netlist and implements the design.
To get a list of all the available xepld command options, type: xepld -help
A complete description of the options is contained on-line in the XEPLD Schematic Design Guide, Appendix D, "Design Implementation and Simulation".
The XC9500 implementation software produces the following output files:
To perform timing simulation on the completed design using Quicksim, execute the following while in the project directory:
xepldsim -mentor <design>
The xepldsim command reads the <design>_tim.xnf
file and translates it to a new Mentor schematic named <design>_tim.
To simulate, invoke Quicksim on the <design>_tim schematic.
Note: With Mentor version B1, GENSCH8
causes problems with XEPLDSIM. Use Mentor version A4 instead.
A complete description of the xepldsim
options is contained on-line in the XEPLD Schematic Design Guide, Appendix
D, "Design Implementation and Simulation".
Autologic Design Flow
This design flow relies on the Xilinx
XC7000 libraries for synthesis and simulation. Designs are synthesized
for an XC7000 device, exported to a Mentor schematic, then implemented
in an XC9500 device.
Step 1: Enter your design in Autologic
and synthesize it wiith XC7000 as the target family.
Step 2: Export a Mentor schematic from
Autologic with the File->Save->EDDM command in the Autologic GUI
using XC7000 as the target family.
Step 3: In a UNIX command window, execute the following command while in the project directory:
xepld <design>
where <design> is the name of
the schematic. The xepld command reads the Mentor schematic file, translates
it to an XNF formatted netlist and implements the design.
To get a list of all the available xepld command options, type: xepld -help
A complete description of the options
is contained on-line in the XEPLD Schematic Design Guide, Appendix D, "Design
Implementation and Simulation".
The XC9500 implementation software produces the following output files:
To perform timing simulation on the
completed design using Quicksim, execute the following while in the project
directory:
xepldsim -mentor <design>
The xepldsim command reads the <design>_tim.xnf file and translates it to a new Mentor schematic named <design>_tim. To simulate, invoke Quicksim on the <design>_tim schematic. A complete description of the xepldsim options is contained on-line in the XEPLD Schematic Design Guide, Appendix D, "Design Implementation and Simulation".
v1.0
Introduction
This application brief shows how to
use Foundation to design with XC9500 CPLDs. System configuration issues
as well as software flows are discussed.
Software Required
XACT-CPLD (DS-560) XC9500 Core Software
FNDT9500.ZIP Foundation XC9500 Interface Patch and Libraries on BBS
Foundation v6.0 Foundation
Note: The Foundation v6.0.1 release
will include the XACT-CPLD CD-ROM. The user will need to install this CD-ROM
to get XC9500 support. However, there is no need to order an additional
DS-560 or use the Foundation XC9500 Interface Patch and Libraries.
System Configuration
XC9500 Only System
Install the XC9500 software and interface
patch into their default directory (c:\xact9000). If you are going to use
XABEL for XC9500 designs, you can install it in its own directory c:\xabel5.
In this installation, your path should include: c:\xact9000;c:\xabel5
The xact variable should be set as
follows: set xact=c:\xact9000;c:\xabel5
XC9500/XC7300/FPGA System
The XC9500 core software and interface
patch should be installed in a separate directory from other Xilinx production
software. This installation will allow you to switch back and forth between
XC9500 and other Xilinx devices by renaming your software directory using
the Window's File Manager.
Install the XC9500 software and interface
patch into their default directory (c:\xact9000). Install the XC7000 and
FPGA core software into a directory named c:\xact6k (not the default directory,
c:\xact). If you are using XABEL, install it into it's own directory named
c:\xabel5
In this installation, your path should include c:\xact;c:\xabel5
The xact variable should be set as
follows: set xact=c:\xact;c:\xabel5
To do XC9500 designs, rename your c:\xact9000 directory to c:\xact
To do designs for any other xilinx device, rename your c:\xact6k directory to c:\xact
Design Flow
Once the XC9500 interface patch is
installed, the standard schematic, ABEL and VHDL design flows can be used
for XC9500 designs. The Foundation output file for the CPLD implementation
tools is <design>.xnf (Foundation automatically does the .PLD
to .XNF file translation for complete chip ABEL designs). Here are some
hints to follow:
1. Remember to add the .ABL or .VHD
source file to your project with the DOCUMENT->ADD command. If you don't,
the Foundation project manager assumes that the top level is a schematic
and the following dialog box will open when you click on the Xilinx implementation
button:
Schematic netlist <design> is older than schematic. Update netlist from Schematic Editor? YES/NO
Be sure to answer NO. If you
answer YES, the XNF file generated by the synthesis process will be overwritten
and the following error message will occur:
Optimizer/Partitioner error when reading the design.xff file:
nd200: [Error] Network ' ' has no primary outputs.
hi7: [Error] Loading the XNF file
failed.
2. You must run the DESIGN->TRANSLATE
process on the XNF file generated by Foundation before implementing the
design. Be sure to uncheck Read Part From Design and select a part using
the Part Selector.
v1.0
Introduction
This application brief shows how to
use Cadence schematic capture and synthesis to design with XC9500 CPLDs.
System configuration issues and software flows are discussed for the Sun
and HP platforms.
Software Required
XACT-CPLD (DS-560) XC9500 Core Software
ver9ksun.tar Backannotated Verilog Output Generator for Sun Platform
ver9khp.tar Backannotated Verilog Output Generator for HP Platform
Cadence Concept v9502 Includes XC7000
Interface and Libraries
The backannotated Verilog output generators are available on the Xilinx BBS and on the Xilinx FTP site.
System Configuration
The XC9500 software should be installed in a separate directory from any other Xilinx production software. When designing with XC9500 devices, this directory should appear in the path statement and XACT environment variable before any other Xilinx software. Assuming each software package is installed it's default directory (/xact9000 for XACT-CPLD and /xact for the Candence XC7000 interface), the UNIX environment variables for the Sun should be: set path = (/xact9000/bin/sparc $path)
setenv XACT /xact9000:$XACT
The UNIX environment variables for the HP700 should be:
set path = (/xact9000/bin/hppa $path)
setenv XACT /xact9000:$XACT
Remember to remove /xact9000 from the
path and XACT environment variable when designing with XC7000 CPLDs or
Xilinx FPGAs.
Schematic Design Flow
This design flow relies on the Xilinx
XC7000 libraries for schematic capture and simulation. To implement a design
for an XC9500 device:
Step 1: Prepare a Cadence schematic
using the XC7000 library symbols provided in the Cadence Interface and
Libraries. Avoid using arithmetic symbols (adders and accumulators) COMPM4
and COMPM8 magnitude comparators, input latches and the BUFCE input register
clock enable buffer since these symbols use XC7000 specific resources.
Step 2: Save the schematic, and follow
the normal design flow for generating an XC7000 XNF file in Cadence.
Step 3: In a UNIX command window, execute the following command while in the project directory:
xepld <design>.xnf
where <design> is the name of
the top level schematic.
To get a list of all the available xepld command options, type: xepld -help
A complete description of the options is contained on-line in the XEPLD Schematic Design Guide, Appendix D, "Design Implementation and Simulation".
The XC9500 implementation software produces the following output files:
To perform timing simulation on the completed design using Verilog XL, execute the following while in the project directory:
xepldsim -verilog <design>
The xepldsim command reads the <design>_tim.xnf
file and generates a structural Verilog HDL file named <design>_tim.v
and an SDF formatted timing backannotation file named <design>_tim.sdf.
A complete description of the xepldsim
options is contained on-line in the XEPLD Schematic Design Guide, Appendix
D, "Design Implementation and Simulation".
Synergy Design Flow
It's unknown if Cadence has implemented an XC7000 synthesis library. If Cadence has implemented this library, then the normal design flow should be used for generating an XC7000 XNF netlist. Once the netlist has been generated, it should be processed as described in Step 3 for schematic designs.
v2.0
Introduction
This application brief shows how to
use Exemplar to design with XC9500 CPLDs. System configuration issues as
well as software flows are discussed.
Software Required
XACT-CPLD (DS-560) XC9500 Core Software
Exemplar Gallileo v3.24 Exemplar Synthesis Tool
XI9.ZIP Exemplar XC9500 Library
XI9.ZIP is available on the Exemplar FTP site for those customers under maintainance:
ftp.exemplar.com/pubs/libraries/xi9.zip
Note: For those customers using the
Model Technology simulator for VHDL timing simulation with Exemplar, XC9500
VITAL models are available from Topdown Design Solutions.
System Configuration
Install the XC9500 software as per
the installation instructions in the XACT-CPLD Release Document. Install
XI9.ZIP as per the instructions provided by Exemplar.
Design Flow
Enter your design in VHDL and process
it as you normally would for a Xilinx CPLD. Exemplar's output file for
the Xilinx CPLD implementation tools is <design>.xnf. This
XC9500 XNF file can be processed by XACT-CPLD and implemented in an XC9500
device.
Note: The Exemplar XC9500 library has not been tested by Xilinx.
© 1996 Xilinx, Inc. All rights reserved
Trademarks and Patents