Configuration

Application Notes

Title	Size
CPLD-Based 1Mbit Virtual SPROM Downloader for XC4000-Series FPGAs	69 kB
FPGA Configuration Guidelines	55 kB
Configuring Mixed FPGA Daisy Chains	24 kB
Configuration Issues: Power-up, Volatility, Security, Battery Back-up	36 kB
Dynamic Reconfiguration	18 kB
Using the XC4000 Readback Capability	60 kB
Boundary Scan in XC4000 and XC5000 Series Devices	111 kB
XC2000 Power Monitoring	24 kB
Configuring FPGAs Over a Processor Bus	541 kB
XC3000 Series Technical Information (CCLK, Powerdown, Startup)	108 kB
Interfacing XC6200 to Microprocessors (TMS320C50 Example)	96 kB
Interfacing XC6200 to Microprocessors (MC68020 Example)	83 kB
Using In-System Programmability in Boundary-Scan Systems	68 kB
Using Automatic Test Equipment to Program XC9500 Devices In-System	67 kB
In-System Programming Times	23 kB
XC9500 In-System Programming Using an 8051 Microcontroller	255 kB
Programming Xilinx XC9500 CPLDs on HP 3070 Testers	79 kB

Title	Size
FastFlash: A New Electrically Erasable CPLD Technology	56 kB

Title	Issue
Programmer Support	Q1 '97
XC9500 ISP on the HP3070 Tester	Q4 '96
Downloading CPLDs with an Embedded Processor	Q4 '96
New CPLD Software Updates, HW-130 Device Programmer Update	Q4 '96
PCI-Based Reconfigurable Computers	Q2 '96
Metalithic System Exploits Real-Time Reconfigurability for Audio Processing	Q1 '96
Sensitivity to Power Glitches	Q4 '95
Readback in FPGAs	Q4 '95
Reconfigurable Computing Developer's Platform	Q4 '95
Xilinx Takes the Lead in ISP Standardization Effort	Q3 '96
In-System Programming and Flash Technology for CPLDs	Q1 '96