DSP Documentation from Xilinx

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FPGA-Based DSP Solutions for '96 (480 kb)
This presentation discusses the following topics: The Xilinx Architecture, DSP Requirements and the Use of FPGAs, Building DSP Functions in FPGAs, Multipliers, FIR Filters, Correlators, Data Routing & Sequencing, Xilinx DSP Case Studies and Design Methodology.

Signal Processing with Xilinx FPGAs (574 kb)
This presentation by Bruce Newgard, Xilinx DSP Field Applications Engineer, discusses the following topics: Distributed Arithmetic (DA), XC4000 Architecture Summary, DA - FIR Filter Example, 8-Tap SLICE, High-Speed FIR, Low-Speed FIR, Decimating FIR, Interpolating FIR, IIR, Biquad, Correlators, Xilinx DSP Case Studies and Design Methodology.

Using Xilinx FPGAs to Design Custom DSPs
This technical paper discusses optimization techniques of digital signal processing algorithms into FPGAs. FPGAs offer both price and performance advantages over traditional off-the-shelf DSP solutions.

16-Tap, 8-Bit FIR Filter Application Note (175 kb)
This application note describes the functionality and integration of a 16-Tap, 8-Bit Finite Impulse Response (FIR) filter macro with predefined coefficients (e.g. low pass) and a sample rate of 5.44 mega-samples per second or 784 MIPS, using an XC4000-4 device. The application note also describes how to set the coefficients of the FIR Filter to meet the needs of other applications. This implementation uses bit-serial Distributed Arithmetic (DA). A parallel implementation operates at over 55 mega-samples per second.

Using Programmable Logic to Accelerate DSP Functions (198 kb)
This paper discusses the benefits of using programmable logic in Digital Signal Processing (DSP) applications. Two case studies--a 16-tap, 8-bit fixed-point FIR filter and a 24-bit Viterbi decoder--demonstrate the advantages of using programmable logic. The summary includes general information on how to decide if programmable logic is best for your DSP application.

Constant Coefficient Multipliers for the XC4000E (114 kb)
This paper identifies two points at which constant coefficient multipliers become the optimum choice in DSP, and implements constant (k) coefficient multipliers (KCMs) in the XC4000E. It also reveals the solution to an interesting design problem which emerges. There are additional enhancements since the original paper, introducing a hybrid technique, was first published in 1993.

A Guide to Using Field Programmable Gate Arrays (FPGAs) for Application-Specific DSP Performance (160 kb)
FPGAs have become a competitive alternative for high-performance DSP applications, previously dominated by general-purpose DSP and ASIC devices. This paper describes the benefits of using an FPGA as a DSP Co-processor, as well as a stand-alone DSP Engine. Two case studies, a Viterbi Decoder Co-processor and a 16-Tap FIR Filter, are used to illustrate how the FPGA can radically accelerate system performance and reduce component count in a DSP application. Finally, different implementation techniques for reducing hardware requirements and increasing performance are described in detail.

Building High Performance FIR Filters Using KCMs (24 kb)
The implementation of digital filters with sample rates above just a few megaHertz are generally difficult and expensive to realize using standard digital signal processors. At this point the potential of distributed arithmetic and parallel processing performed in a Xilinx FPGA becomes the ideal solution. The re-programmable aspect of FPGAs permits optimum use of the available gates in the form of Constant (K) Coefficient Multipliers (KCMs), while enabling the filter to be tuned or changed at any time. Filters employing fully parallel KCMs are ideal for sample rates exceeding 27 MHz with the example able to operate above 50 MHz. This paper identifies the implementation of a Finite Impulse Response Filter using constant (k) coefficient multipliers in the XC4000E.

Block Adaptive Filter (117 kb)
This application note describes a specific design for implementing a high-speed, full-precision, adaptive filter in the XC4000E/EX family of FPGAs. The design may be easily modified, and demonstrates the suitability of using FPGAs in digital signal processing applications. This application note is based on a 12-bit data, 12-bit coefficient, full-precision, block adaptive filter design. This design can be modified to accommodate different data and coefficient sizes, as well as lesser precision. The application note covers how to modify the design including the trade-offs involved. The filter is engineered for use in the XC4000 Series.

FPGAs and DSP (55 kb)
This paper introduces the Xilinx Field Programmable Gate Array (FPGA) technology and helps you understand how FPGAs can be used for DSP system implementation. You will find a comparison of the implementation of a simple DSP function in both Programmable DSP (pDSP) and Gate Array technology. A brief explanation of Gate Array technology is followed by a description of Xilinx FPGA technology.

The Fastest FFT in the West (70 kb)
This paper discusses that the incorporation of a large FFT in a single FPGA, while noteworthy, may evoke a "so what" response. Its speed will be compared to the more standard single-chip DSP design. We propose to compare Xilinx FPGA performance with an exhaustive list of DSP devices. The test benchmark, established in 1995, is the execution time of a 256-point FFT. The speed in the FPGA design is set by the computation time of the radix 2 butterfly. For 16-bit data and a 50 MHz system clock the computation time indicated is 320 ns. The number of butterfly computations ((N/2)log₂N) for a 256-point FFT is:

(256/2)log₂ 256 = 128 x 8 = 1024

The Fastest Filter in the West (29 kb)
This paper discusses the use of Distributed Arithmetic to build faster FIR Filters in FPGAs and compares the performance to other off-the-shelf devices, including the Harris HSP43881. The candidate for this speed challenge is the symmetrical FIR filter; specifically, a programmable 8-tap filter with 8 bits of both coefficient and data values. It is programmable in the sense that its gate resources can be configured to do other tasks. Our adversary is the fixed-point "DSP" chip which, in single precision, processes 16-bit words.

The Role of Distributed Arithmetic in FPGA-based Signal Processing (135 kb)
In this document the Distributed Arithmetic (DA) algorithm is derived and examples are offered that illustrate its effectiveness in producing gate-efficient designs. Distributed Arithmetic plays a key role in embedding DSP functions in the Xilinx XC4000 family of FPGA devices.