The traditional
components used in DSP applications vary depending on the performance requirements
of the application and the complexity of the algorithm. The requirements
of low performance, low complexity applications can be met by standard
microprocessors and microcontrollers. As the performance requirements and/or
complexity of the application increases the designer is forced to look
to higher performance solutions based on single-core DSP microprocessors,
multi-core DSP microprocessors and, ultimately, Function and Algorithm
Specific ICs (FASICs). This is also the domain of the FPGA DSP solution
which uses Distributed Arithmetic techniques in conjunction with
concurrency to achieve astounding performance.
In cases where
a single DSP microprocessor is adequate to the task it is unlikely that
an FPGA will be a good solution primarily due to cost. The FPGA typically
comes into it's own in the higher performance applications where several
single core or multiple core DSP microprocessors are rquired to perform
the function. In these applications the data manipulation function can
typically be performed by one or more FPGAs. Some applications use FPGAs
in conjunction with microprocessors (i.e. the FPGA as a co-processor) since
the flexibility afforded by the presence of a microprocessor is still useful.
Not only is the FPGA capable of performing very high perfoemance tasks,
it can also be a significantly cheaper solution than several high performance
DSP microprocessors, high speed memories, etc.
Xilinx FPGAs are even a viable alternative to FASICs. The turn-around time
of an FPGA is significantly faster than that of an ASIC. This factor combined
with the FPGA's reprogrammability allow the designer to get their high
performance product to market faster. Xilinx also provides the option of
converting your FPGA design to a HardWire
Array, which provide a transparent, no-risk migration path to dramatic
cost reduction without the engineering burden associated with conventional
gate array re-design. This gives the Xilinx FPGA user an extremely high
production volume solution at a competitive cost.
The diagram below shows performance numbers for serial distributed arithmetic
and parallel distributed arithmetic implementations of an 8-tap, 8-bit
FIR filter implemented in Xilinx FPGAs. The serial implementation is fits
in a small device (68% of a 300 gate device) but runs slower than the higher
performance and larger parallel distributed implementations which fit in
88% of a 10,000 gate device or 75% of a 13,000 gate device. The performance
numbers speak for themselves. 
Back to the Xilinx DSP Applications page
