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Fully Compliant PCI Interface in XC3164A-2
FPGA
This application note describes an XC3164A-2 design for a PCI-compliant interface. This implementation uses conservative design practices to guarantee the critical timing paths. The design was created and simulated using Verilog.
16-Tap, 8-Bit FIR Filter Application
Note
This application note describes the functionality and integration of a 16-Tap, 8-Bit Finite Impulse Response (FIR) filter macro with predefined coefficients (e.g. low pass) and a sample rate of 5.44 mega-samples per second or 784 MIPS using an XC4000-4 device. The application note also describes how to set the coefficients of the FIR Filter to meet the needs of other applications.
This technical paper discusses optimization techniques of digital signal processing algorithms into FPGAs. FPGAs offer both price and performance advantages over traditional off-the-shelf DSP solutions.
Using
Programmable Logic to Accelerate DSP Functions (198 kb)
This paper discusses the benefits of using programmable logic in Digital Signal Processing (DSP) applications. Two case studies--a 16-tap, 8-bit fixed-point FIR filter and a 24-bit Viterbi decoder--demonstrate the advantages of using programmable logic. The summary includes general information on how to decide if programmable logic is best for your DSP application.
A
Guide to Using Field Programmable Gate Arrays (FPGAs) for Application-Specific
DSP Performance (160 kb) 
FPGAs have become a competitive alternative for high-performance DSP applications, previously dominated by general-purpose DSP and ASIC devices. This paper describes the benefits of using an FPGA as a DSP Co-processor, as well as a stand-alone DSP Engine. Two case studies, a Viterbi Decoder Co-processor and a 16-Tap FIR Filter, are used to illustrate how the FPGA can radically accelerate system performance and reduce component count in a DSP application. Finally, different implementation techniques for reducing hardware requirements and increasing performance are described in detail.
Building
High Performance FIR Filters Using KCMs (24 kb)
The implementation of digital filters with sample rates above just a few megaHertz are generally difficult and expensive to realize using standard digital signal processors. At this point the potential of distributed arithmetic and parallel processing performed in a Xilinx FPGA becomes the ideal solution. The re-programmable aspect of FPGAs permits optimum use of the available gates in the form of Constant (K) Coefficient Multipliers (KCMs), while enabling the filter to be tuned or changed at any time. Filters employing fully parallel KCMs are ideal for sample rates exceeding 27 MHz with the example able to operate above 50 MHz. This paper identifies the implementation of a Finite Impulse Response Filter using constant (k) coefficient multipliers in the XC4000E.
This paper introduces the Xilinx Field Programmable Gate Array (FPGA) technology and helps you understand how FPGAs can be used for DSP system implementation. You will find a comparison of the implementation of a simple DSP function in both Programmable DSP (pDSP) and Gate Array technology. A brief explanation of Gate Array technology is followed by a description of Xilinx FPGA technology.
The
Fastest FFT in the West (70 kb)
This paper discusses that the incorporation of a large FFT in a single FPGA, while noteworthy, may evoke a "so what" response. Its speed will be compared to the more standard single-chip DSP design. We propose to compare Xilinx FPGA performance with an exhaustive list of DSP devices. The test benchmark, established in 1995, is the execution time of a 256-point FFT. The speed in the FPGA design is set by the computation time of the radix 2 butterfly. For 16-bit data and a 50 MHz system clock the computation time indicated is 320 ns. The number of butterfly computations ((N/2)log2N) for a 256-point FFT is:
(256/2)log2 256 = 128 x 8 = 1024
The
Fastest Filter in the West (29 kb)
This paper discusses the use of Distributed Arithmetic to build faster FIR Filters in FPGAs and compares the performance to other off-the-shelf devices, including the Harris HSP43881. The candidate for this speed challenge is the symmetrical FIR filter; specifically, a programmable 8-tap filter with 8 bits of both coefficient and data values. It is programmable in the sense that its gate resources can be configured to do other tasks. Our adversary is the fixed-point "DSP" chip which, in single precision, processes 16-bit words.
The
Role of Distributed Arithmetic in FPGA-based Signal Processing (135 kb)
In this document the Distributed Arithmetic (DA) algorithm is derived and examples are offered that illustrate its effectiveness in producing gate-efficient designs. Distributed Arithmetic plays a key role in embedding DSP functions in the Xilinx XC4000 family of FPGA devices.
Plug and Play ISA in Xilinx FPGAs
This Application Note describes a Plug and Play ISA interface reference design using a Xilinx XC4003-6PQ100C, or larger, FPGA device. This design implements the features used in a majority of Plug and Play designs but does not implement every option available within the Plug and Play specification.
Dynamic
Microcontroller in XC4000
An application note and design files for a microcontroller with dynamic bus sizing. Uses Xilinx X-BLOX. VIEWlogic design files and a QBASIC-based assembler are available.
Pulse-Width Modulation in Xilinx
An application note and design files for building a pulse-width modulation circuit in Xilinx programmable logic. Uses Xilinx X-BLOX. VIEWlogic design files are included.
C-Cube CL550 and Xilinx XC3020A ISA-based
Motion-JPEG Codec
This design is the result of a collaborative effort between C-Cube Microsystems, Auravision Corporation (Fremont, CA), Xilinx Incorporated (San Jose, CA), and Ring Zero Systems (San Mateo, CA). The design is a Motion-JPEG video codec for ISA bus PC platforms based on the CL550 JPEG, which features a direct hardware interface to the Auravision VxP500 Video Processor.
HDL
Synthesis for FPGAs Design Guide
A designer's guide on how to use Verilog or VHDL effectively with Xilinx programmable logic. Synopsys Design Compiler(tm) and FPGA Compiler(tm) are used in the examples, though the principles apply to most other HDL design packages.
XC5000 Macro Library Supplement
A supplement to the Xilinx Macro Library Guide describing the new and different macros available within the XC5000 design library.
Configuring FPGAs Over a Processor
Bus
This application note describes how to configure an SRAM-based FPGA over a processor bus. It also illustrates the source code required to download a configuration bitstream using an IBM PC as a host microprocessor. 'C' source code is provided. Useful in reconfigurable computing applications.
Voltage Monitoring for XC2000 Devices
All XC5200, XC4000, XC3000, and newer 0.8u XC2000 devices have internal voltage monitoring. A simple circuit provides the equivalent feature for older XC2000 devices.
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